Invention Grant
- Patent Title: Multiple patterning gate scheme for nanosheet rule scaling
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Application No.: US17476136Application Date: 2021-09-15
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Publication No.: US12087771B2Publication Date: 2024-09-10
- Inventor: Lung-Kun Chu , Mao-Lin Huang , Chung-Wei Hsu , Jia-Ni Yu , Chun-Fu Lu , Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238

Abstract:
A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.
Public/Granted literature
- US20220320089A1 MULTIPLE PATTERNING GATE SCHEME FOR NANOSHEET RULE SCALING Public/Granted day:2022-10-06
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