Invention Grant
- Patent Title: Stacked transistor chip package with source coupling
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Application No.: US17485742Application Date: 2021-09-27
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Publication No.: US12094807B2Publication Date: 2024-09-17
- Inventor: Sergey Yuferev , Paul Armand Asentista Calo , Theng Chao Long , Josef Maerz , Chee Yang Ng , Petteri Palm , Wae Chet Yong
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Dicke, Billig & Czaja, PLLC
- Priority: DE 2020127327 2020.10.16
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/31 ; H01L25/00
Abstract:
A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.
Public/Granted literature
- US20220122906A1 STACKED TRANSISTOR CHIP PACKAGE WITH SOURCE COUPLING Public/Granted day:2022-04-21
Information query
IPC分类:
