公开(公告)号：US20210025774A1

公开(公告)日：2021-01-28

申请号：US16890461

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Paul Armand Asentista Calo ,  Chan Lam Cha ,  Kok Yau Chua ,  Jo Ean Chye ,  Chee Hong Lee ,  Swee Kah Lee ,  Theng Chao Long ,  Jayaganasan Narayanasamy ,  Khay Chwan Saw

IPC: G01L9/00 ,  G01L19/14

Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

公开(公告)号：US20180102300A1

公开(公告)日：2018-04-12

申请号：US15784439

申请日：2017-10-16

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long ,  Ming Kai Benny Goh

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

公开(公告)号：US09594111B2

公开(公告)日：2017-03-14

申请号：US13779544

申请日：2013-02-27

Applicant: Infineon Technologies AG

Inventor： Theng Chao Long ,  Nee Wan Khoo

IPC: G01R31/26 ,  G01R31/02 ,  G01R31/28

CPC classification number: G01R31/2601 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2893

Abstract: In one embodiment, a method of testing a semiconductor component includes loading a plurality of semiconductor components into a main turret of a turret handler, transporting the plurality of semiconductor components using the main turret to a test area, and splitting the plurality of semiconductor components into a first set and a second set. The method further includes testing a first semiconductor component in the first set at a first test pad using a tester while transporting a second semiconductor component in the second set to a second test pad and testing the second semiconductor component using the tester while transporting the first semiconductor component out of the first test pad. The first set and the second set are merged into the plurality of semiconductor components and the plurality of semiconductor components are transported away from the test area using the main turret.

Abstract translation: 在一个实施例中，测试半导体部件的方法包括将多个半导体部件加载到转台处理器的主转台中，使用主转台将多个半导体部件传送到测试区域，并将多个半导体部件分成 第一组和第二组。 该方法还包括使用测试仪在第一测试垫中测试第一组中的第一半导体组件，同时将第二组中的第二半导体组件传输到第二测试焊盘，并使用测试仪测试第二半导体组件，同时传送第一半导体 组件出第一个测试板。 第一组和第二组被合并到多个半导体部件中，并且使用主转台将多个半导体部件从测试区域运送出去。

公开(公告)号：US20150348864A1

公开(公告)日：2015-12-03

申请号：US14290046

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long ,  Ming Kai Benny Goh

IPC: H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L29/78 ,  H01L29/739 ,  H01L21/52 ,  H01L21/56 ,  H01L23/46

CPC classification number: H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

Abstract translation: 半导体封装系统包括具有两个或更多个端子的半导体芯片的半导体器件封装以及封装并电绝缘半导体芯片的保护结构。 两个或多个电连接到一个端子的电导体延伸到保护结构的外表面。 第一表面特征在半导体器件封装的外表面上。 该系统还包括可连接的包装扩展器，其具有第二表面特征，该第二表面特征构造成当第一表面特征与第二表面特征配合时与第一表面特征互锁，以便将包装延伸器固定到半导体器件封装。 当包装延伸器固定到半导体器件封装件上时，延伸部分邻接并延伸远离半导体器件封装的外表面。

公开(公告)号：US11274984B2

公开(公告)日：2022-03-15

申请号：US16890461

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Paul Armand Asentista Calo ,  Chan Lam Cha ,  Kok Yau Chua ,  Jo Ean Chye ,  Chee Hong Lee ,  Swee Kah Lee ,  Theng Chao Long ,  Jayaganasan Narayanasamy ,  Khay Chwan Saw

IPC: G01L9/00 ,  G01L19/14

Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

公开(公告)号：US09666557B2

公开(公告)日：2017-05-30

申请号：US13905194

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/00 ,  H01L23/051 ,  H01L23/36 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L25/065 ,  H01L23/051 ,  H01L23/34 ,  H01L23/36 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08237 ,  H01L2224/08257 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73151 ,  H01L2224/73251 ,  H01L2224/80898 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/922 ,  H01L2224/9221 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05 ,  H01L2224/29 ,  H01L2224/80 ,  H01L2924/00012

Abstract: A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

公开(公告)号：US20140353766A1

公开(公告)日：2014-12-04

申请号：US13905194

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L25/065 ,  H01L23/051 ,  H01L23/34 ,  H01L23/36 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08237 ,  H01L2224/08257 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73151 ,  H01L2224/73251 ,  H01L2224/80898 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/922 ,  H01L2224/9221 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05 ,  H01L2224/29 ,  H01L2224/80 ,  H01L2924/00012

Abstract: A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

Abstract translation: 半导体组件包括具有导电区域的衬底和半导体封装。 半导体封装包括半导体管芯，第一和第二端子以及模具化合物。 模具具有相对的第一和第二主表面，垂直于第一和第二主表面设置的边缘，在第一主表面处的第一电极和在第二主表面处的第二电极。 第一端子附接到第一电极。 第二端子附接到第二电极。 模具化合物包围模具和第一和第二端子的至少一部分，使得每个端子具有与模具化合物保持至少部分未覆盖的模具平行并远离模具的一侧。 半导体封装的第一和第二端子连接到衬底的不同的导电区域。

公开(公告)号：US10396018B2

公开(公告)日：2019-08-27

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H02M1/088 ,  H02P27/04

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US09655265B2

公开(公告)日：2017-05-16

申请号：US14287083

申请日：2014-05-26

Applicant: Infineon Technologies AG

Inventor： Tiam Meng Pon ,  Theng Chao Long

IPC: H01R9/00 ,  H05K7/02 ,  H05K3/32 ,  H01L23/64 ,  H01L25/07 ,  H01L23/495 ,  H01L23/50 ,  H01L23/31 ,  H01L23/00

CPC classification number: H05K7/02 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/50 ,  H01L23/64 ,  H01L23/645 ,  H01L24/83 ,  H01L25/07 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/83801 ,  H05K3/32 ,  H05K2203/0703 ,  H05K2203/1305 ,  Y10T29/49131 ,  Y10T29/49147 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An electronic module is provided, comprising an electronic chip arranged in the electronic module and comprising an input terminal and an output terminal; a first current path electrically connected to the input terminal; a second current path electrically connected to the output terminal; and an insulation arranged between the first current path and the second current path, wherein the first current path and the second current path extend in the same direction and arranged in close proximity to each other.

公开(公告)号：US09274163B2

公开(公告)日：2016-03-01

申请号：US13779544

申请日：2013-02-27

Applicant: Infineon Technologies AG

Inventor： Theng Chao Long ,  Nee Wan Khoo

IPC: G01R31/26 ,  G01R31/28

Abstract: In one embodiment, a method of testing a semiconductor component includes loading a plurality of semiconductor components into a main turret of a turret handler, transporting the plurality of semiconductor components using the main turret to a test area, and splitting the plurality of semiconductor components into a first set and a second set. The method further includes testing a first semiconductor component in the first set at a first test pad using a tester while transporting a second semiconductor component in the second set to a second test pad and testing the second semiconductor component using the tester while transporting the first semiconductor component out of the first test pad. The first set and the second set are merged into the plurality of semiconductor components and the plurality of semiconductor components are transported away from the test area using the main turret.