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公开(公告)号:US20250054831A1
公开(公告)日:2025-02-13
申请号:US18785745
申请日:2024-07-26
Applicant: Infineon Technologies AG
Inventor: Chee Yang Ng , Kok Yau Chua , Nurfarena Othman , Milad Mostofizadeh , Joseph Victor Soosai Prakasam
IPC: H01L23/367 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/498 , H01L23/544
Abstract: A method for fabricating one or more semiconductor packages includes: a substrate layer including one or more electrical contact regions; connecting a semiconductor die with one of the electrical contact regions; providing a heat dissipation member including one or more contact areas; attaching a tape to a backside of the heat dissipation member so that opposing ends of the tape extend beyond opposing side edges of the heat dissipation member; connecting a frontside of the heat dissipation member with the semiconductor die by coupling at least one contact area with the semiconductor die; placing a mold tool above the heat dissipation member and the substrate layer with the opposing ends of the tape extending out of the mold tool so that the tape is removable from outside the mold tool; filling an encapsulant into the mold cavity; and removing the tape.
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公开(公告)号:US12094807B2
公开(公告)日:2024-09-17
申请号:US17485742
申请日:2021-09-27
Applicant: Infineon Technologies AG
Inventor: Sergey Yuferev , Paul Armand Asentista Calo , Theng Chao Long , Josef Maerz , Chee Yang Ng , Petteri Palm , Wae Chet Yong
IPC: H01L23/495 , H01L23/31 , H01L25/00
CPC classification number: H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L25/50
Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.
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公开(公告)号:US20180148322A1
公开(公告)日:2018-05-31
申请号:US15692938
申请日:2017-08-31
Applicant: Infineon Technologies AG
Inventor: Dominic Maier , Matthias Steiert , Chau Fatt Chiang , Christian Geissler , Bernd Goller , Thomas Kilger , Johannes Lodermeyer , Franz-Xaver Muehlbauer , Chee Yang Ng , Beng Keh See , Claus Waechter
Abstract: A semiconductor package includes a semiconductor die having a sensor structure disposed at a first side of the semiconductor die, and a first port extending through the semiconductor die from the first side to a second side of the semiconductor die opposite the first side, so as to provide a link to the outside environment. Corresponding methods of manufacture are also provided.
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公开(公告)号:US20170275159A1
公开(公告)日:2017-09-28
申请号:US15079593
申请日:2016-03-24
Applicant: Infineon Technologies AG
Inventor: Chau Fatt Chiang , Kok Yau Chua , Swee Kah Lee , Chee Yang Ng , Horst Theuss
IPC: B81C1/00 , B81B7/00 , H01L23/498 , H01L21/48 , H01L23/552
CPC classification number: B81C1/00333 , B81B7/0064 , B81C2203/019 , H01L21/4857 , H01L21/486 , H01L21/4878 , H01L23/10 , H01L23/498 , H01L23/49822 , H01L23/49861 , H01L23/552
Abstract: A base plate with a first side having an elevated portion, a recessed portion laterally surrounding the elevated portion, and a vertical face extending from the recessed portion to the elevated portion is provided. At least a part of the vertical face is covered with a metal layer. A mold compound structure is formed on the first side with the metal layer disposed between the first side and the mold compound structure such that the mold compound structure includes an elevated portion laterally surrounding a recessed portion, and opposing edge faces that vertically extend from the recessed portion to the elevated portion. At least a part of the base plate is subsequently removed such that the recessed portion of the mold compound structure is uncovered from the base plate and such that the metal layer remains on at least one uncovered section of the mold compound structure.
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公开(公告)号:US11984392B2
公开(公告)日:2024-05-14
申请号:US17459296
申请日:2021-08-27
Applicant: Infineon Technologies AG
Inventor: Chee Yang Ng , Stefan Woetzel , Edward Fuergut , Thai Kee Gan , Chee Hong Lee , Jayaganasan Narayanasamy , Ralf Otremba
IPC: H01L23/498 , H01L23/00 , H01L23/373 , H01L23/492 , H01L23/538 , H01L29/66 , H01L23/31
CPC classification number: H01L23/49844 , H01L23/3735 , H01L23/4924 , H01L23/5383 , H01L24/05 , H01L24/08 , H01L24/14 , H01L24/16 , H01L29/66431 , H01L23/3185 , H01L23/49827 , H01L24/06 , H01L24/32 , H01L2224/0556 , H01L2224/0603 , H01L2224/06181 , H01L2224/32227 , H01L2924/13055 , H01L2924/13064 , H01L2924/13091
Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
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公开(公告)号:US20230052437A1
公开(公告)日:2023-02-16
申请号:US17973920
申请日:2022-10-26
Applicant: Infineon Technologies AG
Inventor: Stefan Woetzel , Chee Yang Ng
IPC: H01L23/31 , H01L23/538
Abstract: A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.
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公开(公告)号:US20200154183A1
公开(公告)日:2020-05-14
申请号:US16682468
申请日:2019-11-13
Applicant: Infineon Technologies AG
Inventor: Kok Yau Chua , Chee Yang Ng
Abstract: In accordance with an embodiment a package includes: a package structure which defines inner surfaces delimiting an inner volume and outer surfaces directed towards an exterior of the package; at least one acoustic sensor element applied to at least one of the inner surfaces, to convert acoustic waves arriving from the exterior of the package into acoustic information in the form of electric signals; a plurality of millimeter wave sensing elements applied to at least one of the outer surfaces, to receive reflected radar signals from objects in the exterior of the package; and a circuitry applied to at least one of the inner surfaces of the package structure, wherein the circuitry is electrically connected to the at least one acoustic sensor element and the plurality of millimeter wave sensing elements to process the acoustic information and the reflected radar signals.
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公开(公告)号:US09868632B2
公开(公告)日:2018-01-16
申请号:US15079593
申请日:2016-03-24
Applicant: Infineon Technologies AG
Inventor: Chau Fatt Chiang , Kok Yau Chua , Swee Kah Lee , Chee Yang Ng , Horst Theuss
IPC: H01L21/48 , B81C1/00 , H01L23/552 , H01L23/498 , B81B7/00
CPC classification number: B81C1/00333 , B81B7/0064 , B81C2203/019 , H01L21/4857 , H01L21/486 , H01L21/4878 , H01L23/10 , H01L23/498 , H01L23/49822 , H01L23/49861 , H01L23/552
Abstract: A base plate with a first side having an elevated portion, a recessed portion laterally surrounding the elevated portion, and a vertical face extending from the recessed portion to the elevated portion is provided. At least a part of the vertical face is covered with a metal layer. A mold compound structure is formed on the first side with the metal layer disposed between the first side and the mold compound structure such that the mold compound structure includes an elevated portion laterally surrounding a recessed portion, and opposing edge faces that vertically extend from the recessed portion to the elevated portion. At least a part of the base plate is subsequently removed such that the recessed portion of the mold compound structure is uncovered from the base plate and such that the metal layer remains on at least one uncovered section of the mold compound structure.
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公开(公告)号:US20150145107A1
公开(公告)日:2015-05-28
申请号:US14089971
申请日:2013-11-26
Applicant: Infineon Technologies AG
Inventor: Chee Yang Ng
IPC: H01L23/552 , H01L23/00 , H01L21/3205 , H01L23/31 , H01L21/56
CPC classification number: H01L23/552 , H01L21/561 , H01L21/568 , H01L23/295 , H01L23/3121 , H01L23/49541 , H01L23/66 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2223/6677 , H01L2224/04105 , H01L2224/0557 , H01L2224/06051 , H01L2224/06187 , H01L2224/12105 , H01L2224/94 , H01L2225/06513 , H01L2924/12042 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2224/03 , H01L2924/00 , H01L2224/27
Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area.
Abstract translation: 半导体器件包括具有第一主表面,与第一主表面相对的第二主表面和侧壁表面的半导体芯片。 电接触区域在半导体芯片的侧壁表面露出。 导电层至少部分地覆盖第二主表面和电接触区域。
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公开(公告)号:US20150145078A1
公开(公告)日:2015-05-28
申请号:US14090019
申请日:2013-11-26
Applicant: Infineon Technologies AG
Inventor: Chee Yang Ng
CPC classification number: H01L23/315 , B81C1/00269 , B81C99/002 , B81C2203/0109 , H01L2224/16 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor package includes a semiconductor die having a first main side and a second main side opposite the first main side, the first main side having an inner region surrounded by a periphery region. The semiconductor package further includes a film covering the semiconductor die and adhered to the periphery region of the first main side of the semiconductor die. The film has a curved surface so that the inner region of the first main side of the semiconductor die is spaced apart from the film by an air gap. Electrical conductors are attached at a first end to pads at the periphery region of the first main side of the semiconductor die. A corresponding method of manufacture is also provided.
Abstract translation: 半导体封装包括具有第一主侧和与第一主侧相对的第二主侧的半导体管芯,第一主侧具有由周边区域包围的内部区域。 半导体封装还包括覆盖半导体管芯并粘附到半导体管芯的第一主侧的周边区域的膜。 薄膜具有弯曲表面,使得半导体管芯的第一主侧的内部区域与膜间隔开气隙。 电导体在第一端附接到半导体管芯的第一主侧的周边区域处的焊盘。 还提供了相应的制造方法。
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