公开(公告)号：US20220028840A1

公开(公告)日：2022-01-27

申请号：US17384217

申请日：2021-07-23

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Sergey Yuferev

IPC: H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64 ,  H01L25/18 ,  H01L25/00

Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.

公开(公告)号：US12094807B2

公开(公告)日：2024-09-17

申请号：US17485742

申请日：2021-09-27

Applicant: Infineon Technologies AG

Inventor： Sergey Yuferev ,  Paul Armand Asentista Calo ,  Theng Chao Long ,  Josef Maerz ,  Chee Yang Ng ,  Petteri Palm ,  Wae Chet Yong

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L25/50

Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

公开(公告)号：US11935874B2

公开(公告)日：2024-03-19

申请号：US17384217

申请日：2021-07-23

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Sergey Yuferev

IPC: H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/072 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/642 ,  H01L25/18 ,  H01L25/50

Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.