Invention Grant
- Patent Title: Fin-type field effect transistor having a wrap-around gate with bottom isolation and inner spacers to reduce parasitic capacitance
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Application No.: US17484019Application Date: 2021-09-24
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Publication No.: US12094949B2Publication Date: 2024-09-17
- Inventor: Choonghyun Lee , Chanro Park , Ruilong Xie , Kangguo Cheng
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: CANTOR COLBURN LLP
- Agent Samuel Waldbaum
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/02 ; H01L21/28 ; H01L29/06 ; H01L29/66 ; H01L29/786

Abstract:
Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.
Public/Granted literature
Information query
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