Invention Grant
- Patent Title: Semiconductor device with linear capacitance
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Application No.: US17225531Application Date: 2021-04-08
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Publication No.: US12113061B2Publication Date: 2024-10-08
- Inventor: Tomas Palacios , Nadim Chowdhury , Qingyun Xie
- Applicant: Massachusetts Institute of Technology
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institute of Technology
- Current Assignee: Massachusetts Institute of Technology
- Current Assignee Address: US MA Cambridge
- Agency: DALY, CROWLEY, MOFFORD & DURKEE, LLP
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L29/20 ; H01L29/205 ; H01L29/778

Abstract:
A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes.
Public/Granted literature
- US20210343703A1 SEMICONDUCTOR DEVICE WITH LINEAR PARASITIC CAPACITANCE Public/Granted day:2021-11-04
Information query
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