公开(公告)号：US12113061B2

公开(公告)日：2024-10-08

申请号：US17225531

申请日：2021-04-08

Applicant: Massachusetts Institute of Technology

Inventor： Tomas Palacios ,  Nadim Chowdhury ,  Qingyun Xie

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes.