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公开(公告)号：US20190390950A1
公开(公告)日：2019-12-26
申请号：US16449410
申请日：2019-06-23
Applicant: Massachusetts Institute of Technology
Inventor： Yuxuan Lin , Xiang Ji , Tomas Palacios , Jing Kong
Abstract: A thermo-mechanical bolometer includes a substrate and a sensing component mounted on the substrate. The sensing element comprises (a) at least one thermal-actuation component mounted in parallel with the substrate and (b) a strain sensor mounted on the at least one layer of thermal-actuation component. The at least one thermal-actuation component alone or in combination (a) absorbs electromagnetic waves and converts energy from absorbed electromagnetic waves into a change in temperature and (b) converts the change in temperature into a deformation of the at least one layer. The strain sensor comprises a layer of fragments with a gap space between the fragments, wherein the strain sensor senses the deformation or mechanical movement and exhibits a change in electrical resistance in response to the sensed deformation or mechanical movement.
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公开(公告)号：US20240162105A1
公开(公告)日：2024-05-16
申请号：US18548704
申请日：2022-03-29
Applicant: Massachusetts Institute of Technology
Inventor： Tomas Palacios , Ahmad Zubair , John Niroula
IPC: H01L23/31 , H01L29/20 , H01L29/778 , H01L29/78 , H01L29/861 , H01L29/872
CPC classification number: H01L23/3192 , H01L23/3171 , H01L29/2003 , H01L29/7786 , H01L29/7813 , H01L29/7827 , H01L29/8613 , H01L29/872 , H01L29/8725
Abstract: A semiconductor device having an electric field management layer. The electric field management layer comprises a material with a relatively high dielectric constant that minimizes the risk of an electric field within the semiconductor device breaking down and damaging the semiconductor device.
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公开(公告)号：US20200027745A1
公开(公告)日：2020-01-23
申请号：US16219300
申请日：2018-12-13
Inventor： William J. Gallagher , Marinus Johannes Petrus Hopstaken , Ko-Tao Lee , Tomas Palacios , Daniel Piedra , Devendra K. Sadana
IPC: H01L21/306 , H01L21/02
Abstract: A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
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公开(公告)号：US10217641B2
公开(公告)日：2019-02-26
申请号：US15001957
申请日：2016-01-20
Inventor： William J. Gallagher , Marinus Johannes Petrus Hopstaken , Ko-Tao Lee , Tomas Palacios , Daniel Piedra , Devendra K. Sadana
IPC: H01L29/778 , H01L21/306 , H01L21/02 , H01L29/207 , H01L29/10 , H01L29/20
Abstract: A GaN device is formed on a semiconductor substrate having a plurality of recessed regions formed in a surface thereof. A seed layer, optional buffer layer, and gallium nitride layer such as a carbon-doped gallium nitride layer are successively deposited within the recessed regions. Improved current collapse response of the GaN device is attributed to maximum length and width dimensions of the multilayer stack.
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公开(公告)号：US20240405147A1
公开(公告)日：2024-12-05
申请号：US18627725
申请日：2024-04-05
Applicant: Massachusetts Institute of Technology
Inventor： Tomas Palacios , Jung-Han Hsia
IPC: H01L31/113 , H01L31/028 , H01L31/0304 , H01L31/0312 , H01L31/032 , H01L31/0352
Abstract: Described herein is a semiconductor structure, comprising: a drain region; a drift region comprised of a wide band gap material disposed over the drain region; and a channel structure disposed over the drift region. In some embodiments, the channel structure comprises: an optically active material disposed over the drift region, wherein the optically active material generates charge carriers in response to an optical signal; and a source region disposed over the optically active material, wherein in an off state charge carriers in the optically active material are depleted to turn off the semiconductor structure, and in an on state charge carriers in the optically active material conduct a current in the semiconductor structure when an electric field is applied across the source region and drain region, causing the current to substantially flow directly between the source region and the drain region.
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Patent Agency Ranking
公开(公告)号：US20160284811A1
公开(公告)日：2016-09-29
申请号：US15034051
申请日：2014-11-04
Applicant: Massachusetts Institute of Technology
Inventor： Lili Yu , Han Wang , Tomas Palacios
IPC: H01L29/45 , H01L29/786 , H01L21/3205 , H01L21/3215 , H01L21/285 , H01L21/288
CPC classification number: H01L29/45 , H01B1/04 , H01L21/28506 , H01L21/288 , H01L21/32055 , H01L21/3215 , H01L29/1606 , H01L29/413 , H01L29/454 , H01L29/456 , H01L29/786 , H01L29/861
Abstract: Device are described that include a semiconductor material layer and at least one graphene-based electrode disposed over a portion of the semiconductor material layer, such that the at least one graphene-based electrode forms an overlap region with the semiconductor material layer. The device includes a means for providing charge carriers in the at least one graphene-based electrode proximate to the overlap region, to reduce a difference between a work function of the at least one graphene-based electrode and an electron affinity of the semiconductor material layer, to reduce a Schottky barrier height between the semiconductor material layer and the at least one graphene-based electrode.
Abstract translation: 描述了包括半导体材料层和设置在半导体材料层的一部分上的至少一个基于石墨烯的电极的装置，使得至少一个基于石墨烯的电极与半导体材料层形成重叠区域。 该器件包括用于在靠近重叠区域的至少一个基于石墨烯的电极中提供电荷载体的装置，以减少至少一个基于石墨烯的电极的功函数与半导体材料层的电子亲和力之间的差异 以降低半导体材料层和至少一个基于石墨烯的电极之间的肖特基势垒高度。
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公开(公告)号：US12232864B2
公开(公告)日：2025-02-25
申请号：US17226564
申请日：2021-04-09
Applicant: Massachusetts Institute of Technology
Inventor： Wojciech Matusik , Antonio Torralba , Michael J. Foshey , Wan Shou , Yiyue Luo , Pratyusha Sharma , Yunzhu Li , Tomas Palacios
Abstract: Systems and methods are provided for estimating 3D poses of a subject based on tactile interactions with the ground. Test subject interactions with the ground are recorded using a sensor system along with reference information (e.g., synchronized video information) for use in correlating tactile information with specific 3D poses, e.g., by training a neural network based on the reference information. Then, tactile information received in response to a given subject interacting with the ground can be used to estimate the 3D pose of the given subject directly, i.e., without reference to corresponding reference information. Certain exemplary embodiments use a sensor system in the form of a pressure sensing carpet or mat, although other types of sensor systems using pressure or other sensors can be used in various alternative embodiments.
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公开(公告)号：US12176454B1
公开(公告)日：2024-12-24
申请号：US18627725
申请日：2024-04-05
Applicant: Massachusetts Institute of Technology
Inventor： Tomas Palacios , Jung-Han Hsia
IPC: H01L31/11 , H01L31/0352 , H01L31/113 , H01L31/028 , H01L31/0304 , H01L31/0312 , H01L31/032
Abstract: Described herein is a semiconductor structure, comprising: a drain region; a drift region comprised of a wide band gap material disposed over the drain region; and a channel structure disposed over the drift region. In some embodiments, the channel structure comprises: an optically active material disposed over the drift region, wherein the optically active material generates charge carriers in response to an optical signal; and a source region disposed over the optically active material, wherein in an off state charge carriers in the optically active material are depleted to turn off the semiconductor structure, and in an on state charge carriers in the optically active material conduct a current in the semiconductor structure when an electric field is applied across the source region and drain region, causing the current to substantially flow directly between the source region and the drain region.
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公开(公告)号：US12113061B2
公开(公告)日：2024-10-08
申请号：US17225531
申请日：2021-04-08
Applicant: Massachusetts Institute of Technology
Inventor： Tomas Palacios , Nadim Chowdhury , Qingyun Xie
IPC: H01L27/06 , H01L29/20 , H01L29/205 , H01L29/778
CPC classification number: H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/7786
Abstract: A semiconductor device having relatively linear and constant parasitic capacitance of an operation range includes a first component having a negatively charged carrier channel and a second component comprising a positively charged carrier channel. The first component has source terminal and a drain terminal. The second component has bias terminal. Both components share a gate terminal that is electrostatically coupled to the negatively charged carrier channel of the first component and the positively charged carrier channel of the second component to produce a capacitance profile that stays relatively linear and constant as a voltage at the gate terminal changes.
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公开(公告)号：US10914637B2
公开(公告)日：2021-02-09
申请号：US16449410
申请日：2019-06-23
Applicant: Massachusetts Institute of Technology
Inventor： Yuxuan Lin , Xiang Ji , Tomas Palacios , Jing Kong
Abstract: A thermo-mechanical bolometer includes a substrate and a sensing component mounted on the substrate. The sensing element comprises (a) at least one thermal-actuation component mounted in parallel with the substrate and (b) a strain sensor mounted on the at least one layer of thermal-actuation component. The at least one thermal-actuation component alone or in combination (a) absorbs electromagnetic waves and converts energy from absorbed electromagnetic waves into a change in temperature and (b) converts the change in temperature into a deformation of the at least one layer. The strain sensor comprises a layer of fragments with a gap space between the fragments, wherein the strain sensor senses the deformation or mechanical movement and exhibits a change in electrical resistance in response to the sensed deformation or mechanical movement.
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