Invention Grant
- Patent Title: MRAM circuit structure and layout structure
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Application No.: US17368848Application Date: 2021-07-07
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Publication No.: US12178052B2Publication Date: 2024-12-24
- Inventor: Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN202110598874.1 20210531
- Main IPC: H10B61/00
- IPC: H10B61/00 ; H10N50/80

Abstract:
A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.
Public/Granted literature
- US20220384523A1 MRAM CIRCUIT STRUCTURE AND LAYOUT STRUCTURE Public/Granted day:2022-12-01
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