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公开(公告)号：US20250072007A1
公开(公告)日：2025-02-27
申请号：US18946884
申请日：2024-11-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.
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公开(公告)号：US11955154B2
公开(公告)日：2024-04-09
申请号：US17744746
申请日：2022-05-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yi-Ting Wu , Yung-Ching Hsieh , Jian-Jhong Chen , Chia-Wei Lee
CPC classification number: G11C11/1673
Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
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3.发明公开公开(公告)号：US20230282260A1
公开(公告)日：2023-09-07
申请号：US17701703
申请日：2022-03-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jian-Jhong Chen , Yi-Ting Wu , Jen-Yu Wang , Cheng-Tung Huang , Po-Chun Yang , Yung-Ching Hsieh
CPC classification number: G11C11/161 , H01L43/02 , H01L43/12 , H01L43/10 , H01L43/08 , H01L27/222
Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
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公开(公告)号：US20220263012A1
公开(公告)日：2022-08-18
申请号：US17735094
申请日：2022-05-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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公开(公告)号：US11903325B2
公开(公告)日：2024-02-13
申请号：US17735094
申请日：2022-05-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
CPC classification number: H10N50/80 , G11C11/161 , G11C11/1659 , H10B61/22 , G11C11/1673 , G11C11/1675 , H10N50/85
Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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Patent Agency Ranking
公开(公告)号：US20210313509A1
公开(公告)日：2021-10-07
申请号：US16852542
申请日：2020-04-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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公开(公告)号：US10978122B1
公开(公告)日：2021-04-13
申请号：US16796953
申请日：2020-02-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Yu-Tse Kuo , Chang-Hung Chen , Shu-Ru Wang , Ya-Lan Chiou , Chun-Hsien Huang , Chih-Wei Tsai , Hsin-Chih Yu , Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Jhen-Siang Wu , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
Abstract: A memory includes (n−1) non-volatile cells, (n−1) bit lines and a current driving circuit. Each of the (n−1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n−1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n−1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n−1) non-volatile cells.
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公开(公告)号：US12178052B2
公开(公告)日：2024-12-24
申请号：US17368848
申请日：2021-07-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.
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9.发明授权公开(公告)号：US11942130B2
公开(公告)日：2024-03-26
申请号：US17701703
申请日：2022-03-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jian-Jhong Chen , Yi-Ting Wu , Jen-Yu Wang , Cheng-Tung Huang , Po-Chun Yang , Yung-Ching Hsieh
CPC classification number: G11C11/161 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85 , G11C11/15 , G11C11/165
Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
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公开(公告)号：US11355695B2
公开(公告)日：2022-06-07
申请号：US16852542
申请日：2020-04-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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