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公开(公告)号：US11903325B2
公开(公告)日：2024-02-13
申请号：US17735094
申请日：2022-05-02
发明人： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
CPC分类号： H10N50/80 , G11C11/161 , G11C11/1659 , H10B61/22 , G11C11/1673 , G11C11/1675 , H10N50/85
摘要： A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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公开(公告)号：US11637103B2
公开(公告)日：2023-04-25
申请号：US17492687
申请日：2021-10-04
发明人： Yen-Wei Tung , Jen-Yu Wang , Cheng-Tung Huang , Yan-Jou Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/06 , H01L27/02 , H01L29/78 , H01L29/49 , H01L29/51 , H01L29/423 , H01L29/165 , H01L21/8238 , H01L21/3213 , H01L21/762 , H01L21/02
摘要： A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.
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公开(公告)号：US20210313509A1
公开(公告)日：2021-10-07
申请号：US16852542
申请日：2020-04-19
发明人： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
摘要： A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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公开(公告)号：US10978122B1
公开(公告)日：2021-04-13
申请号：US16796953
申请日：2020-02-21
发明人： Chun-Yen Tseng , Yu-Tse Kuo , Chang-Hung Chen , Shu-Ru Wang , Ya-Lan Chiou , Chun-Hsien Huang , Chih-Wei Tsai , Hsin-Chih Yu , Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Jhen-Siang Wu , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
摘要： A memory includes (n−1) non-volatile cells, (n−1) bit lines and a current driving circuit. Each of the (n−1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n−1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n−1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n−1) non-volatile cells.
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公开(公告)号：US20160003888A1
公开(公告)日：2016-01-07
申请号：US14321841
申请日：2014-07-02
发明人： Wen-Yin Weng , Wei-Heng Hsu , Cheng-Tung Huang , Yi-Ting Wu , Yu-Ming Lin , Jen-Yu Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.
摘要翻译： 可以使用表征器件的方法来根据器件的阈值电压，体效应和氧化物电容来确定器件的金属功函数。 可以根据电流 - 电压曲线来确定阈值电压。 可以根据电容器对电压曲线来确定氧化物电容。
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6.发明授权公开(公告)号：US11942130B2
公开(公告)日：2024-03-26
申请号：US17701703
申请日：2022-03-23
发明人： Jian-Jhong Chen , Yi-Ting Wu , Jen-Yu Wang , Cheng-Tung Huang , Po-Chun Yang , Yung-Ching Hsieh
CPC分类号： G11C11/161 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85 , G11C11/15 , G11C11/165
摘要： A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
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公开(公告)号：US11355695B2
公开(公告)日：2022-06-07
申请号：US16852542
申请日：2020-04-19
发明人： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
摘要： A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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公开(公告)号：US11238912B1
公开(公告)日：2022-02-01
申请号：US17146424
申请日：2021-01-11
发明人： Yi-Ting Wu , Cheng-Tung Huang , Jen-Yu Wang , Yung-Ching Hsieh , Po-Chun Yang , Jian-Jhong Chen , Bo-Chang Li
摘要： In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.
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公开(公告)号：US20210183944A1
公开(公告)日：2021-06-17
申请号：US16746974
申请日：2020-01-20
发明人： Yi-Ting Wu , Jian-Jhong Chen , Po-Chun Yang , Jhen-Siang Wu , Yung-Ching Hsieh , Bo-Chang Li , Jen-Yu Wang , Cheng-Tung Huang
摘要： A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.
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公开(公告)号：US10056463B2
公开(公告)日：2018-08-21
申请号：US15628592
申请日：2017-06-20
发明人： Su Xing , Hsueh-Wen Wang , Chien-Yu Ko , Yu-Cheng Tung , Jen-Yu Wang , Cheng-Tung Huang , Yu-Ming Lin
IPC分类号： H01L21/28 , H01L29/51 , H01L29/786 , H01L29/66 , H01L27/11585
CPC分类号： H01L29/516 , H01L27/11585 , H01L29/40111 , H01L29/42376 , H01L29/4908 , H01L29/66545 , H01L29/6684 , H01L29/66969 , H01L29/7869
摘要： A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.
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