Invention Grant
- Patent Title: Stacked varistor
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Application No.: US17907267Application Date: 2021-03-18
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Publication No.: US12183491B2Publication Date: 2024-12-31
- Inventor: Masashi Takamura , Ken Yanai , Sayaka Watanabe , Tomomitsu Muraishi
- Applicant: Panasonic Intellectual Property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: Panasonic Intellectual Property Management Co., Ltd.
- Current Assignee: Panasonic Intellectual Property Management Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Rimon P.C.
- Priority: JP2020-088513 20200521
- International Application: PCT/JP2021/011063 WO 20210318
- International Announcement: WO2021/235071 WO 20211125
- Main IPC: H01C7/18
- IPC: H01C7/18 ; H01C7/112 ; H01G4/30 ; H01G4/40

Abstract:
A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.
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