公开(公告)号：US12106877B2

公开(公告)日：2024-10-01

申请号：US17768271

申请日：2020-09-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Sayaka Matsumoto ,  Ken Yanai ,  Masashi Takamura ,  Masaya Hattori ,  Tomomitsu Muraishi

IPC: H01C1/14 ,  H01C7/10 ,  H01C7/18

CPC classification number: H01C1/14 ,  H01C7/10 ,  H01C7/18

Abstract: It is aimed to provide a laminated varistor capable of reducing stray capacitance to occur between an internal electrode and an external electrode, and also capable of reducing a variation in the stray capacitance due to a variation in the external electrode. A laminated varistor of the present disclosure has external electrodes on first end surface, second end surface, and first side surface of sintered body. No external electrode is provided on second side surface opposite to first side surface. Varistor regions in which internal electrodes overlap each other in a laminating direction are provided at positions closer to second side surface than to first side surface.

公开(公告)号：US12224090B2

公开(公告)日：2025-02-11

申请号：US17796143

申请日：2021-12-17

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masashi Takamura ,  Sayaka Watanabe ,  Takeshi Fujii ,  Ken Yanai ,  Yuto Akiyama

IPC: H01C7/105 ,  H01C1/148

Abstract: A multilayer varistor has a stack structure including a plurality of layers stacked in a third direction. The multilayer varistor includes a first internal electrode electrically connected to a first external electrode, a second internal electrode electrically connected to the second external electrode, and a third internal electrode electrically connected to the third external electrode. The first internal electrode is disposed between the second internal electrode and the third internal electrode in the third direction.

公开(公告)号：US12183491B2

公开(公告)日：2024-12-31

申请号：US17907267

申请日：2021-03-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masashi Takamura ,  Ken Yanai ,  Sayaka Watanabe ,  Tomomitsu Muraishi

IPC: H01C7/18 ,  H01C7/112 ,  H01G4/30 ,  H01G4/40

Abstract: A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.