Invention Grant
- Patent Title: Semiconductor package and method of manufacturing the same
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Application No.: US17884037Application Date: 2022-08-09
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Publication No.: US12255079B2Publication Date: 2025-03-18
- Inventor: Chin-Chuan Chang , Szu-Wei Lu , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/56 ; H01L21/78 ; H01L23/00 ; H01L25/065

Abstract:
A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. Corresponding structures result from these methods.
Public/Granted literature
- US20220384212A1 Semiconductor Package and Method of Manufacturing The Same Public/Granted day:2022-12-01
Information query
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