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公开(公告)号:US11929261B2
公开(公告)日:2024-03-12
申请号:US17097857
申请日:2020-11-13
发明人: Chin-Chuan Chang , Szu-Wei Lu , Chen-Hua Yu
IPC分类号: H01L21/56 , H01L21/78 , H01L23/00 , H01L23/538 , H01L25/065
CPC分类号: H01L21/561 , H01L21/568 , H01L21/78 , H01L23/5389 , H01L24/05 , H01L24/13 , H01L25/0655 , H01L2224/0233 , H01L2224/02379 , H01L2224/04105 , H01L2924/15311 , H01L2924/181
摘要: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.
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公开(公告)号:US20220384212A1
公开(公告)日:2022-12-01
申请号:US17884037
申请日:2022-08-09
发明人: Chin-Chuan Chang , Szu-Wei Lu , Chen-Hua Yu
IPC分类号: H01L21/56 , H01L23/538 , H01L25/065 , H01L23/00 , H01L21/78
摘要: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages. Corresponding structures result from these methods.
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公开(公告)号:US20200176337A1
公开(公告)日:2020-06-04
申请号:US16420186
申请日:2019-05-23
发明人: Yi-Chao Mao , Chin-Chuan Chang , Szu-Wei Lu
IPC分类号: H01L21/66 , H01L21/56 , H01L21/306
摘要: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.
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公开(公告)号:US10672631B2
公开(公告)日:2020-06-02
申请号:US16103933
申请日:2018-08-15
发明人: Yi-Chao Mao , Chin-Chuan Chang , Szu-Wei Lu
IPC分类号: H01L21/67 , H01L23/00 , H01L21/683 , H01L21/687 , H01L21/56
摘要: A method and a system for thinning a substrate are provided. The method includes at least the following steps. A liquid seal is provided at an interface between a chuck and a substrate disposed on the chuck. The substrate is thinned during the liquid seal is provided.
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公开(公告)号:US20240128157A9
公开(公告)日:2024-04-18
申请号:US17872750
申请日:2022-07-25
发明人: Chin-Chuan Chang , Szu-Wei Lu , Chen-Hua Yu
IPC分类号: H01L23/48 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/498 , H01L25/065 , H01L25/10
CPC分类号: H01L23/481 , H01L21/561 , H01L21/563 , H01L21/76898 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L23/49822 , H01L24/48 , H01L2224/08235 , H01L2224/16148 , H01L2224/32145 , H01L2224/48229 , H01L2224/73204 , H01L2224/95001 , H01L2225/06513 , H01L2225/06524 , H01L2225/06544 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/182 , H01L2924/37001
摘要: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The first side of the substrate is attached to a carrier. The substrate is thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the substrate. A device die is bonded to the second connectors. The substrate is singulated into multiple packages.
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公开(公告)号:US11515288B2
公开(公告)日:2022-11-29
申请号:US16934631
申请日:2020-07-21
发明人: Chin-Chuan Chang , Tsei-Chung Fu , Jing-Cheng Lin
IPC分类号: H01L21/56 , H01L23/00 , H01L23/522 , H01L23/31
摘要: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.
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公开(公告)号:US11469218B2
公开(公告)日:2022-10-11
申请号:US17073888
申请日:2020-10-19
发明人: Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC分类号: H01L25/065 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/498 , H01L25/00
摘要: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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公开(公告)号:US11094635B2
公开(公告)日:2021-08-17
申请号:US16548202
申请日:2019-08-22
发明人: Chin-Chuan Chang , Szu-Wei Lu
IPC分类号: H01L23/538 , H01L25/065 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56 , H01L21/78 , H01L21/683 , H01L25/00
摘要: A package structure is provided. The package structure includes a first redistribution structure and an interposer over the first redistribution structure. The package structure also includes a molding compound layer surrounding the interposer, and a second redistribution structure over the interposer. The molding compound layer is between the first redistribution structure and the second redistribution structure. The package structure further includes a first semiconductor die and a second semiconductor die over the second redistribution structure.
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公开(公告)号:US11056364B2
公开(公告)日:2021-07-06
申请号:US16886800
申请日:2020-05-29
发明人: Yi-Chao Mao , Chin-Chuan Chang , Szu-Wei Lu
IPC分类号: H01L21/67 , H01L23/00 , H01L21/683 , H01L21/687 , H01L21/56
摘要: A method for thinning a substrate is provided. The method includes at least the following steps. A substrate is disposed on a carrying surface of a chuck, where a first liquid supply unit surrounds the chuck to form a frame of the chuck, and an outlet of the first liquid supply unit is disposed aside the carrying surface of the chuck. A first liquid flows from a bottom of the frame to the outlet and discharges to fill a gap between the substrate and the carrying surface of the chuck. The substrate is thinned during the gap is filled.
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公开(公告)号:US10672723B2
公开(公告)日:2020-06-02
申请号:US16392815
申请日:2019-04-24
发明人: Jing-Cheng Lin , Chin-Chuan Chang , Jui-Pin Hung
IPC分类号: H01L23/00 , H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L25/03 , H01L25/00 , H01L25/065 , H01L25/10
摘要: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.
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