Invention Grant
- Patent Title: Metallization stacks with self-aligned staggered metal lines
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Application No.: US17017735Application Date: 2020-09-11
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Publication No.: US12261114B2Publication Date: 2025-03-25
- Inventor: Elijah V. Karpov , Christopher J. Jezewski , Manish Chandhok , Nafees A. Kabir , Matthew V. Metz
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/522

Abstract:
Methods for fabricating metallization stacks with one or more self-aligned staggered metal lines, and related semiconductor devices, are disclosed. Methods and devices are based on providing a spacer material conformal to bottom metal lines of a first layer of a metallization stack. By carefully designing parameters of the deposition process, the spacer material may be deposited in such a manner that, for each pair of adjacent bottom metal lines of the first layer, an opening in the spacer material is formed in a layer above the bottom metal lines (i.e., in the second layer of the metallization stack), the opening being substantially equidistant to the adjacent bottom metal lines of the first layer. Top metal lines are formed by filling the openings with an electrically conductive material, resulting in the top metal lines being self-aligned and staggered with respect to the bottom metal lines.
Public/Granted literature
- US20220084942A1 METALLIZATION STACKS WITH SELF-ALIGNED STAGGERED METAL LINES Public/Granted day:2022-03-17
Information query
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