Invention Application
- Patent Title: Low power clock distribution methodology
- Patent Title (中): 低功率时钟分配方法
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Application No.: US10113052Application Date: 2002-04-01
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Publication No.: US20020190775A1Publication Date: 2002-12-19
- Inventor: Hidetaka Magoshi
- Applicant: Sony Computer Entertainment America Inc.
- Applicant Address: CA Foster City
- Assignee: Sony Computer Entertainment America Inc.
- Current Assignee: Sony Computer Entertainment America Inc.
- Current Assignee Address: CA Foster City
- Main IPC: G06F001/04
- IPC: G06F001/04
Abstract:
A semiconductor device includes a transmission line bounded by a first buffer and a second buffer. The first and second buffers are placed such that the transmission line has a length between a minimum and a maximum, thereby permitting narrow clock signal pulses to be transmitted with reduced distortion.
Public/Granted literature
- US06667647B2 Low power clock distribution methodology Public/Granted day:2003-12-23
Information query
