公开(公告)号：US20030052343A1

公开(公告)日：2003-03-20

申请号：US10278197

申请日：2002-10-22

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: H01L027/148

CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/1506 ,  H03L7/07 ,  H03L7/0814

Abstract: A semiconductor chip includes a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each being operable to produce a respective output clock signal from an associated input clock signal in accordance with an error signal, the outputs of a subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the clock buffers adjust the respective output clock signals in accordance with the respective error signals.

公开(公告)号：US20040003178A1

公开(公告)日：2004-01-01

申请号：US10187072

申请日：2002-07-01

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/02

CPC classification number: G06F12/0875 ,  G06F12/0862

Abstract: Methods and apparatus enable: the partitioning of a main memory into a plurality of blocks, each block being adjacent to at least one of the other blocks, and each block including a plurality of data units containing one or more bits of data; the partitioning of each block of the main memory into a plurality of zones, each zone containing one or more of the data units; the association of at least some of the respective zones of each given block with respective others of the adjacent blocks to the given block; and the pre-fetching of a given one of the other blocks into a cache memory when any one of the data units within any of the associated zones of that block is addressed.

Abstract translation: 方法和装置使得能够将主存储器划分成多个块，每个块与至少一个其它块相邻，并且每个块包括包含一个或多个数据位的多个数据单元; 将主存储器的每个块划分成多个区域，每个区域包含一个或多个数据单元; 每个给定块的相应区域中的至少一些区域与相邻块的相应块的关联到给定块; 以及在该块的任何相关联的区域内的任何一个数据单元被寻址时，将其他块中的给定一个块预取入高速缓冲存储器。

公开(公告)号：US20030208661A1

公开(公告)日：2003-11-06

申请号：US10187150

申请日：2002-07-01

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/00

CPC classification number: G06F9/3824 ,  G06F9/30043 ,  G06F9/3885 ,  G06F12/0888 ,  G06F12/126 ,  G06F12/127

Abstract: Methods and apparatus for controlling a cache memory are described in which the overwriting of floating point data into any cache line of the cache memory is prohibited when the data stored in such cache line are valid, integer data.

Abstract translation: 描述了用于控制高速缓冲存储器的方法和装置，其中当存储在这种高速缓存行中的数据有效时，将浮点数据重写到高速缓存存储器的任何高速缓存行中是有效的，整数数据。

公开(公告)号：US20030177343A1

公开(公告)日：2003-09-18

申请号：US10202355

申请日：2002-07-24

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F009/00

CPC classification number: G06F15/8053 ,  A63F2300/203 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3885

Abstract: A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.

Abstract translation: 提供了多处理计算机体系结构及其操作方法。 多处理架构提供了主处理器和多个子处理器级联在一起以有效地执行循环操作。 主处理器执行循环外的操作并控制循环。 多个子处理器可操作地互连，并且由主处理器分配给给定的循环迭代。 每个子处理器可操作以顺序地接收一个或多个子指令，对每个子指令进行操作，并将子指令传播到后续的子处理器。

公开(公告)号：US20020190775A1

公开(公告)日：2002-12-19

申请号：US10113052

申请日：2002-04-01

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F001/04

CPC classification number: G06F1/10

Abstract: A semiconductor device includes a transmission line bounded by a first buffer and a second buffer. The first and second buffers are placed such that the transmission line has a length between a minimum and a maximum, thereby permitting narrow clock signal pulses to be transmitted with reduced distortion.

Abstract translation: 半导体器件包括由第一缓冲器和第二缓冲器限定的传输线。 放置第一和第二缓冲器使得传输线具有最小和最大值之间的长度，从而允许以较小的失真传输窄时钟信号脉冲。

公开(公告)号：US20030229800A1

公开(公告)日：2003-12-11

申请号：US10245946

申请日：2002-09-18

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/14

CPC classification number: G06F21/73 ,  G06F21/50

Abstract: Methods and apparatus for producing an electronic ID number include modifying at least one physical bit element from among each of at least first and second groups of physical bit elements, each physical bit element of each group having a first physical state in which it is operable to produce a signal having a first electrical state, and being capable of permanent modification to a second physical state in which it is operable to produce a signal having a second electrical state; and producing (i) one bit of an identification (ID) number from the respective signals issuing from each of the respective at least first and second groups of physical bit elements, and (ii) a validity signal indicative of whether the one bit of the ID number is valid.

Abstract translation: 用于产生电子ID号码的方法和装置包括从至少第一和第二组物理比特元素中的每一个中修改至少一个物理比特元素，每组的每个物理比特元素具有第一物理状态，其中可操作 产生具有第一电状态的信号，并且能够永久地修改为可操作以产生具有第二电状态的信号的第二物理状态; 以及从相应的至少第一和第二组物理位元素中的每一个发出的相应信号产生（i）一位识别（ID）号码，以及（ii）指示所述至少一个位 身份证号码有效。

公开(公告)号：US20030226026A1

公开(公告)日：2003-12-04

申请号：US10246501

申请日：2002-09-18

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/14

CPC classification number: G06F21/79 ,  G06F21/10 ,  G06F2221/0744

Abstract: Methods and apparatus permit: reading a rewritable storage medium, the rewritable storage medium including digital content and a flag indicative of whether the digital content is encrypted; determining whether the digital content of the rewritable storage medium is encrypted based on the flag; encrypting the digital content of the rewritable storage medium using an identification (ID) number as an encryption key when the flag indicates that the digital content is not encrypted, the ID number being unique to a processing apparatus operable to execute the digital content; and overwriting the digital content of the rewritable storage medium with the encrypted digital content.

Abstract translation: 方法和装置允许：读取可重写存储介质，包括数字内容的可重写存储介质和指示数字内容是否被加密的标志; 基于所述标志来确定所述可重写存储介质的数字内容是否被加密; 当所述标志指示所述数字内容未加密时，使用识别（ID）号作为加密密钥对所述可重写存储介质的数字内容进行加密，所述ID号对于可执行数字内容的处理装置是唯一的; 并用加密的数字内容覆盖可重写存储介质的数字内容。

公开(公告)号：US20030208658A1

公开(公告)日：2003-11-06

申请号：US10228347

申请日：2002-08-26

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F012/00

CPC classification number: G06F12/0811 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0897

Abstract: Methods and apparatus for controlling hierarchical cache memories permit: controlling a first level cache memory including a plurality of cache lines, each cache line being operable to store an address tag and data; controlling a next lower level cache memory including a plurality of cache lines, each cache line being operable to store an address tag, status flags, and data, the status flags of each cache line including an L-flag; and setting the L-flag of a given cache line of the next lower level cache memory to indicate whether or not a corresponding one the of the cache lines of the first level cache memory has been refilled with a copy of the data stored in the given cache line of the next lower level cache memory.

Abstract translation: 用于控制分层缓存存储器的方法和装置允许：控制包括多个高速缓存行的第一级高速缓存存储器，每条高速缓存行可操作地存储地址标签和数据; 控制包括多个高速缓存行的下一个较低级高速缓冲存储器，每条高速缓存行可操作以存储地址标签，状态标志和数据，每个高速缓存行的状态标志包括一个L标记; 以及设置下一个较低级高速缓冲存储器的给定高速缓存行的L标志，以指示第一级高速缓冲存储器的高速缓存行中的相应一条高速缓冲存储器是否已经被重新填充存储在给定的数据中的数据的副本 缓存行的下一级缓存内存。

公开(公告)号：US20030182541A1

公开(公告)日：2003-09-25

申请号：US10200790

申请日：2002-07-22

Applicant: Sony Computer Entertainment America Inc.

Inventor： Hidetaka Magoshi

IPC: G06F009/00

CPC classification number: G06F9/3885 ,  G06F9/30069

Abstract: Methods and apparatus in accordance with the present invention enable introducing a plurality of instructions into respective stages in a multistage processing pipeline; and prohibiting execution of only those one or more instructions already in the pipeline that should be skipped to effect a forward branch.

Abstract translation: 根据本发明的方法和装置能够将多个指令引入到多级处理流水线中的各个级中; 并且禁止仅执行已经在流水线中应该被跳过以实现前向分支的那些一个或多个指令。