Invention Application
US20030020104A1 Increased efficiency semiconductor devices including intermetallic layer
审中-公开
提高半导体器件的效率,包括金属间化合物层
- Patent Title: Increased efficiency semiconductor devices including intermetallic layer
- Patent Title (中): 提高半导体器件的效率,包括金属间化合物层
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Application No.: US09911484Application Date: 2001-07-25
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Publication No.: US20030020104A1Publication Date: 2003-01-30
- Inventor: Albert A. Talin , Alexander A. Demkov , Paige M. Holm
- Applicant: MOTOROLA, INC.
- Applicant Address: IL Schaumburg
- Assignee: MOTOROLA, INC.
- Current Assignee: MOTOROLA, INC.
- Current Assignee Address: IL Schaumburg
- Main IPC: H01L031/0328
- IPC: H01L031/0328 ; H01L021/336 ; H01L029/76

Abstract:
High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Dual gate field effect transistors exhibiting increased transconductance are fabricated using planar processing techniques.
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