公开(公告)号：US20030017661A1

公开(公告)日：2003-01-23

申请号：US09910018

申请日：2001-07-23

Applicant: MOTOROLA, INC.

Inventor： Ravindranath Droopad ,  Albert A. Talin ,  Barbara F. Barenburg ,  Lyndee L. Hilt

IPC: H01L021/337

CPC classification number: H01L21/268 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

Abstract: Semiconductor structures are provided with high quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates such as large silicon wafers utilizing a compliant substrate. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and an overlying monocrystalline material layer. With laser assisted fabrication, a laser energy source is used to preclean the accommodating buffer layer, to excite the accommodating buffer layer to higher energy to promote two-dimensional growth, and to amorphize the accommodating buffer layer, without requiring transport of the semiconductor structure from one environment to another. When chemical vapor deposition is utilized, the laser radiation source can also be employed to crack volatile chemical precursors and to enable selective deposition.

Abstract translation: 半导体结构设置有在单晶衬底上生长的单晶材料的高质量外延层，例如使用顺应衬底的大硅晶片。 实现顺应性衬底的形成的一种方式包括首先在硅晶片上生长容纳缓冲层。 容纳缓冲层与下面的硅晶片和上覆单晶材料层晶格匹配。 通过激光辅助制造，使用激光能量源来清除容纳缓冲层，将容纳缓冲层激发到更高的能量以促进二维生长，并使收容缓冲层非晶化，而不需要将半导体结构从 一个环境到另一个环境。 当使用化学气相沉积时，也可以使用激光辐射源来破坏挥发性化学前体并实现选择性沉积。

公开(公告)号：US20030015714A1

公开(公告)日：2003-01-23

申请号：US09910021

申请日：2001-07-23

Applicant: MOTOROLA, INC.

Inventor： Albert A. Talin

IPC: H01L029/06

CPC classification number: H01L21/02197 ,  C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02348 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02694 ,  H01L21/2686 ,  H01L21/31691

Abstract: Process for fabricating a semiconductor structure (33), and the resulting structure (33), comprising forming a perovskite oxide film (241) overlying an monocrystalline silicon substrate (22) and an amorphous oxide interface layer (28), which is then surface treated with photonic emissions, such as ultraviolet radiation, effective to eliminate and desorb water at the surface of the perovskite oxide film (241). Subsequently, a monocrystalline compound semiconductor layer (26) is formed overlying the surface-treated perovskite oxide film (241).

Abstract translation: 制造半导体结构（33）的方法和所得结构（33）包括形成覆盖在单晶硅衬底（22）和无定形氧化物界面层（28）上的钙钛矿氧化物膜（241），然后将其表面处理 具有诸如紫外辐射的光子发射，有效地消除和解吸在钙钛矿氧化物膜（241）的表面处的水。 随后，形成覆盖表面处理的钙钛矿氧化物膜（241）的单晶化合物半导体层（26）。

公开(公告)号：US20030020104A1

公开(公告)日：2003-01-30

申请号：US09911484

申请日：2001-07-25

Applicant: MOTOROLA, INC.

Inventor： Albert A. Talin ,  Alexander A. Demkov ,  Paige M. Holm

IPC: H01L031/0328 ,  H01L021/336 ,  H01L029/76

CPC classification number: H01L27/0688 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0605 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Dual gate field effect transistors exhibiting increased transconductance are fabricated using planar processing techniques.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 表现出增加的跨导的双栅场效应晶体管使用平面处理技术制造。

公开(公告)号：US20030015770A1

公开(公告)日：2003-01-23

申请号：US09908897

申请日：2001-07-20

Applicant: MOTOROLA, INC.

Inventor： Albert A. Talin ,  Barbara F. Barenburg

IPC: H01L029/06

CPC classification number: G02B6/132 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/1215

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Trenches in composite integrated circuits are provided that may be used for electrical isolation and strain relief. The trenches may also be implemented as optical waveguides to carry optical signals on- or off-chip.

Abstract translation: 通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶化合物半导体层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 提供复合集成电路中的沟槽，可用于电气隔离和应变消除。 沟槽也可以实现为光波导，以承载或片外的光信号。

公开(公告)号：US20030042147A1

公开(公告)日：2003-03-06

申请号：US09942496

申请日：2001-08-29

Applicant: Motorola, Inc.

Inventor： Albert A. Talin ,  Bernard F. Coll ,  Kenneth A. Dean ,  Matthew Stainer

IPC: C25D015/00 ,  C25D005/10 ,  C25D003/56

CPC classification number: B82Y15/00 ,  B01J21/04 ,  B01J21/10 ,  B01J23/38 ,  B01J23/58 ,  B01J23/745 ,  B01J23/78 ,  B01J35/0013 ,  B01J37/348 ,  B82Y10/00 ,  C25D7/00 ,  H01J2201/30469 ,  Y10S977/835 ,  Y10S977/843 ,  Y10S977/847

Abstract: Methods of forming a nano-supported catalyst on a substrate and at least one carbon nanotube on the substrate are comprised of configuring a substrate with an electrode (102), immersing the substrate with the electrode into a solvent containing a first metal salt and a second metal salt (104) and applying a bias voltage to the electrode such that a nano-supported catalyst is at least partly formed with the first metal salt and the second metal salt on the substrate at the electrode (106). In addition, the method of forming at least one carbon nanotube is comprised of conducting a chemical reaction process such as catalytic decomposition, pyrolysis, chemical vapor deposition, or hot filament chemical vapor deposition o grow at least one nanotube on the surface of the nano-supported catalyst (108).

Abstract translation: 在基板上形成纳米载体的催化剂和在基板上形成至少一个碳纳米管的方法包括用电极（102）构成基板，将基板与电极浸入含有第一金属盐和第二金属的溶剂 金属盐（104），并向所述电极施加偏置电压，使得纳米载体催化剂至少部分地与所述电极（106）上的所述基底上的所述第一金属盐和所述第二金属盐形成。 此外，形成至少一个碳纳米管的方法包括进行化学反应过程如催化分解，热解，化学气相沉积或热丝化学气相沉积o在纳米级表面上生长至少一个纳米管， 负载型催化剂（108）。

公开(公告)号：US20030015760A1

公开(公告)日：2003-01-23

申请号：US09908695

申请日：2001-07-20

Applicant: Motorola, Inc.

Inventor： Jay A. Curless ,  Albert A. Talin

IPC: H01L021/8238 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L21/8258 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/31691 ,  H01L21/324

Abstract: Process for fabricating a semiconductor structure (500) comprising depositing a capping layer (67) on a portion (54) of a monocrystalline compound semiconductor layer (66) overlying a template film (64), a monocrystalline perovskite oxide material (60), an amorphous oxide layer (62) and a monocrystalline silicon substrate (52), and then exposing at least one surface region (531) of the single crystal silicon substrate (52) into which a CMOS circuit (56) is formed in a CMOS region (53), followed by heating the CMOS circuit (56) to anneal the CMOS region (53) and, optionally, concurrently transform the monocrystalline perovskite oxide film (60) into an amorphous perovskite oxide film (136). The resulting composite semiconductor structure (500) is also encompassed.

Abstract translation: 一种用于制造半导体结构（500）的方法，包括在覆盖在模板膜（64）上的单晶化合物半导体层（66）的一部分（54）上沉积覆盖层（67），单晶钙钛矿氧化物材料（60）， 非晶氧化物层（62）和单晶硅衬底（52），然后暴露在CMOS区域中形成有CMOS电路（56）的单晶硅衬底（52）的至少一个表面区域（531） 53），然后加热CMOS电路（56）以退火CMOS区域（53），并且任选地同时将单晶钙钛矿氧化物膜（60）转变成无定形钙钛矿氧化物膜（136）。 所得的复合半导体结构（500）也包括在内。

公开(公告)号：US20030015731A1

公开(公告)日：2003-01-23

申请号：US09910020

申请日：2001-07-23

Applicant: Motorola, Inc.

Inventor： Jay A. Curless ,  Lyndee L. Hilt ,  Albert A. Talin

IPC: H01L031/109

CPC classification number: H01L21/31691 ,  H01L21/02197 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521

Abstract: Process for fabricating a semiconductor structure (34), and the resulting products, having reduced crystal defects and/or contamination in a monocrystalline compound semiconductor layer (26) that is compliantly attached to a monocrystalline semiconductor substrate (22) via an accommodating buffer layer (36), a capping/template layer (30), and a thin monocrystalline compound semiconductor seed film (38) comprised of a compound semiconductor, in that order from furthest to closest to layer (26). To accomplish this, a thin monocrystalline compound semiconductor seed film (38) is formed on an intermediate structure (33) including a monocrystalline perovskite buffer layer (24) and an overlying capping/template layer (30), and the resulting structure (33) is annealed at a temperature effective to reduce crystal defects in the compound semiconductor seed film (38), and optionally also may be used to amorphize the monocrystalline perovskite layer, all before a compound semiconductor layer (26) is formed thereon in a device-thickness.

Abstract translation: 制造半导体结构（34）的方法以及所得产品具有通过容纳缓冲层顺应地附接到单晶半导体衬底（22）的单晶化合物半导体层（26）中具有减小的晶体缺陷和/或污染 36），封盖/模板层（30）和由化合物半导体构成的薄单晶化合物半导体种子膜（38），其从最远到最靠近层（26）的顺序。 为了实现这一点，在包括单晶钙钛矿缓冲层（24）和上覆盖/模板层（30）的中间结构（33）上形成薄单晶化合物半导体种子膜（38），所得结构（33） 在有效地减少化合物半导体种子膜（38）中的晶体缺陷的温度下进行退火，并且任选地还可以将其用于非晶化单晶钙钛矿层，所有这些都是在其上形成化合物半导体层（26）之前的器件厚度 。

公开(公告)号：US20030015711A1

公开(公告)日：2003-01-23

申请号：US09908892

申请日：2001-07-20

Applicant: Motorola, Inc.

Inventor： Albert A. Talin ,  Lyndee L. Hilt ,  Alexander A. Demkov

IPC: H01L029/04

CPC classification number: H01L27/0605 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate includes utilizing an intermetallic layer of an intermetallic compound material.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成包括利用金属间化合物材料的金属间化合物层。