公开(公告)号：US20040251483A1

公开(公告)日：2004-12-16

申请号：US10836878

申请日：2004-04-30

Inventor： Cheng C. Ko ,  Barry Levine

IPC: H01L031/0328

CPC classification number: H01L31/1075 ,  H01L31/035281 ,  Y02E10/50

Abstract: A planar avalanche photodiode includes a small localized contact layer on the top of the device produced by either a diffusion or etching process and a semiconductor layer defining a lower contact area. A semiconductor multiplication layer is positioned between the two contact areas and a semiconductor absorption layer is positioned between the multiplication layer and the upper contact layer. The photodiode has a low capacitance and a low field near the edges of the semiconductor multiplication and absorption layers.

Abstract translation: 平面雪崩光电二极管包括通过扩散或蚀刻工艺产生的器件的顶部上的小的局部接触层和限定较低接触面积的半导体层。 半导体倍增层位于两个接触区域之间，半导体吸收层位于倍增层和上接触层之间。 光电二极管在半导体乘法吸收层的边缘附近具有低电容和低电场。

公开(公告)号：US20040235295A1

公开(公告)日：2004-11-25

申请号：US10442759

申请日：2003-05-20

Inventor： Zhong Dong ,  Chuck Jang ,  Chia-Shun Hsiao

IPC: H01L031/0328

CPC classification number: H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28158 ,  H01L21/3105 ,  H01L21/31612

Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825null C. to about 950null C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.

Abstract translation: 公开了一种方法和装置，用于降低通过化学气相沉积（CVD）形成的半导体氧化物组合物中的氯和/或其它结合的污染物的浓度，所述半导体氧化物组合物使用提供半导体元素的反应物如二氯硅烷（DCS）和氧 提供反应物如N2O。 在一个实施方案中，通过将N 2 O气体加热至约825℃至约950℃的温度来退火DCS-HTO膜，以引发N2O气体的放热分解并使加热的气体流过 DCS-HTO膜，使得加热的N2O气体内的分解的原子氧自由基能够将分离能转移到结合在DCS-HTO膜内的氯原子，从而原子氧自由基可以填充DCS-HTO的半导体氧化物基体内的氧空位 电影。 可以用退火的DCS-HTO膜形成改进的ONO结构，用于浮动栅极或其他存储器应用中。

公开(公告)号：US20040227157A1

公开(公告)日：2004-11-18

申请号：US10437530

申请日：2003-05-13

Applicant: Newport Fab, LLC dba Jazz Semiconductor

Inventor： Gregory D. U'Ren ,  Sy Vo

IPC: H01L031/0328

CPC classification number: H01L21/8249 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661

Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

Abstract translation: 所公开的实施例是用于制造SiGe层的方法，所述方法包括在第一压力下在单结晶区域和至少一个隔离区域上沉积硅缓冲层，其中硅缓冲层是连续的，即包括小的多晶粒， 在所述至少一个隔离区域上。 该方法还包括在第二压力下在硅缓冲层上形成硅锗层，其中硅锗层在至少一个隔离区域上也是连续的，即包含小的多晶粒。 在一个实施例中，第一压力小于第二压力。 在其他实施例中，根据上述方法制造结构。

公开(公告)号：US20040212044A1

公开(公告)日：2004-10-28

申请号：US10833142

申请日：2004-04-28

Inventor： Atsushi Kurokawa ,  Masao Yamane ,  Yoshinori Imamura

IPC: H01L031/0328

CPC classification number: H01L29/7371 ,  H01L29/1004 ,  H01L29/66318

Abstract: A bipolar transistor having the enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have the enhanced characteristics.

Abstract translation: 具有增强特性的双极晶体管通过蚀刻形成在发射极台面（上部发射极层）和基底电极下方的基底台面而制成，以便在其大致矩形区域的边缘上具有突起区域。 形成掩模膜例如绝缘膜以覆盖矩形区域和突起区域，并且通过使用绝缘膜作为掩模蚀刻基底层以形成基底台面。 因此，可以防止在基极和发射极台面彼此面对的区域的边缘上的基极和发射极台面发生异常蚀刻，并且可以防止基极层和发射极层之间的电阻的增加。 由此双极晶体管可以具有增强的特性。

公开(公告)号：US20040211979A1

公开(公告)日：2004-10-28

申请号：US10824080

申请日：2004-04-14

Applicant: Konica Minolta Holdings, Inc.

Inventor： Kazuyoshi Shioiri ,  Tetsuya Yoshida ,  Yuusuke Kawahara ,  Kazuyoshi Ichikawa

IPC: H01L031/0328

CPC classification number: H05K1/0233 ,  H05K1/095 ,  H05K3/0023 ,  H05K3/1241 ,  H05K3/28 ,  H05K3/386 ,  H05K2201/0723

Abstract: A circuit board includes a base material, a conductive pattern which is formed on the base material, and a resin layer which is formed on the conductive pattern by a photocurable resin.

Abstract translation: 电路板包括基材，形成在基材上的导电图案和通过光固化树脂形成在导电图案上的树脂层。

公开(公告)号：US20040211978A1

公开(公告)日：2004-10-28

申请号：US10805309

申请日：2004-03-22

Inventor： Junichiro Kobayashi

IPC: H01L031/0328

CPC classification number: H01L29/7371 ,  H01L29/42304 ,  H01L29/732

Abstract: A semiconductor device, able to be produced while suppressing the occurrence of mesa shaped abnormalities without restriction as to the pattern layout, the type of etchant used, etc., provided with a semiconductor mesa portion including a stack of a collector layer, a base layer, and an emitter layer on a substrate and functioning as an active region of a bipolar transistor, a base contact pad mesa portion separated from this by a predetermined distance and having a height the same as the top surface of the base layer, and a conductor layer integrally formed with a base electrode connected to the base layer, a base contact pad electrode formed on the base contact pad mesa portion in a region other than near the edges of the top surface of the base contact pad mesa portion, and an interconnect connecting these, and a method of producing the same.

Abstract translation: 一种半导体器件，能够在不限制图案布局，所用蚀刻剂的类型等的同时抑制台面形异常的发生而被制造，该半导体器件设置有包括集电极层的堆叠的半导体台面部分，基底层 以及作为双极型晶体管的有源区域起作用的基板上的发射极层，从该基极接触垫台面部分与基极层的顶面相隔预定距离并具有相同高度的基极接触垫台面部分， 与基底层连接的基底电极一体形成的基底接触焊盘电极，形成在基底接触垫台面部分上的基部接触焊盘台面部分之外的区域，而不是靠近基底接触垫台面部分的顶面的边​​缘， 这些及其制造方法。

公开(公告)号：US20040195588A1

公开(公告)日：2004-10-07

申请号：US10626526

申请日：2003-07-25

Inventor： Ichiro Hase

IPC: H01L031/0328 ,  H01L031/0336 ,  H01L031/072

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66318

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III-V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of nnull-GaAs, a collector layer made of nnull-GaAs, a base layer made of pnull-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of nnull-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract translation: 提供了具有改进特性的异质结双极晶体管（HBT）。 将其中添加有Bi的III-V族化合物半导体用于基于GaAs或InP的HBT的基极层。 例如，通过依次堆叠由n + GaAs构成的子集电极层，由n + GaAs制成的集电极层，由p + GaAsBi制成的基极层，形成GaAs基HBT， 由n-InGaP制成的发射极层，由n-GaAs制成的第一覆盖层，以及由单晶GaAs制成的衬底1上由n + -InGaAs制成的第二覆盖层。

公开(公告)号：US20040195586A1

公开(公告)日：2004-10-07

申请号：US10156408

申请日：2002-05-28

Inventor： Hisamitsu Suzuki

IPC: H01L031/0328

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L23/485

Abstract: A semiconductor device raises the maximum oscillation frequency fmax of the bipolar transistor. The stopper dielectric layer is formed on the substrate to cover the transistor section and the isolation dielectric. The interlayer dielectric layer is formed on the stopper dielectric layer. The base contact plug, which is formed in the interlayer dielectric layer, is located over the isolation dielectric in such a way as to contact the graft base region near its bottom end corner. Therefore, the base contact needs not to entirely overlap with the graft base region, which means that the graft base region can be narrowed without increasing the base resistance Rb and that the collector-base capacitance Ccb is reduced. Also, electrical short circuit between the graft base region and the collector region can be effectively suppressed by the stopper dielectric layer.

Abstract translation: 半导体器件提高双极晶体管的最大振荡频率fmax。 阻挡介电层形成在衬底上以覆盖晶体管部分和隔离电介质。 层间绝缘层形成在阻挡电介质层上。 形成在层间电介质层中的基极接触插塞位于隔离电介质的上方，以便接近其底端拐角附近的移植基底区域。 因此，基底接触不需要与移植物基底区域完全重叠，这意味着接枝基底区域可以变窄而不增加基极电阻Rb，并且集电极 - 基极电容Ccb减小。 此外，可以通过阻挡介电层有效地抑制接枝基极区域和集电极区域之间的电短路。

公开(公告)号：US20040195585A1

公开(公告)日：2004-10-07

申请号：US10729426

申请日：2003-12-05

Applicant: University of Massachusetts Lowell ,  M/A-COM

Inventor： Samson Mil'shtein ,  Peter Ersland ,  Shivarajiv Kumar Somisetty ,  Carlos Gil

IPC: H01L031/0328

CPC classification number: H01L29/7783 ,  H01L29/42316

Abstract: A heterostructured field effect transistor has a multi-gate configuration, in which the gate voltages are individually biased to tailor the potential field. The multi-gate configuration can be a two-, three-, or four-gate configuration. The transconductance of the transistor can be substantially linear over a range of gate voltages.

Abstract translation: 异质结场效应晶体管具有多栅极配置，其中栅极电压被单独偏置以调整势场。 多门配置可以是二，三或四门配置。 晶体管的跨导在栅极电压的范围上可以是基本上线性的。

公开(公告)号：US20040188712A1

公开(公告)日：2004-09-30

申请号：US10820343

申请日：2004-04-07

Applicant: EiC Corporation

Inventor： Chien Ping Lee ,  Frank Hin Fai Chau ,  Nanlei Larry Wang ,  Clarence John Dunnrowicz ,  Yan Chen ,  Barry Jia-Fu Lin

IPC: H01L031/0328

CPC classification number: H01L29/0821 ,  H01L29/7371

Abstract: The safe-operating area (SOA) in a heterojunction bipolar transistor (HBT) is improved by providing a collector region in the transistor having a graded (continuous or stepped) doping between the base region and the underlying subcollector region with the collector doping being lowest near the base and highest near the subcollector and with the collector doping being less than the doping of the subcollector. The non-uniformly doped collector reduces Kirk effect induced breakdown when collector current increases.

Abstract translation: 在异质结双极晶体管（HBT）中的安全工作区域（SOA）通过在晶体管中提供集电极区域来改善，晶体管在基极区域和下面的子集电极区域之间具有渐变（连续或阶梯）掺杂，集电极掺杂最低 靠近基极并且在子集电极附近最高，并且集电极掺杂小于子集电极的掺杂。 当集电极电流增加时，非均匀掺杂的集电极会降低Kirk效应引起的击穿。