发明申请
- 专利标题: Semiconductor integrated circuit device
- 专利标题(中): 半导体集成电路器件
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申请号: US10946000申请日: 2004-09-22
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公开(公告)号: US20050035428A1公开(公告)日: 2005-02-17
- 发明人: Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
- 申请人: Norikatsu Takaura , Riichiro Takemura , Hideyuki Matsuoka , Shinichiro Kimura , Hisao Asakura , Ryo Nagai , Satoru Yamada
- 专利权人: Hitachi, Ltd.,Elpida Memory, Inc.
- 当前专利权人: Hitachi, Ltd.,Elpida Memory, Inc.
- 优先权: JP2001-382942 20011217
- 主分类号: H01L21/76
- IPC分类号: H01L21/76 ; H01L21/8238 ; H01L21/8242 ; H01L27/08 ; H01L27/092 ; H01L27/105 ; H01L27/108 ; H01L29/76
摘要:
A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.
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