公开(公告)号：US20050035428A1

公开(公告)日：2005-02-17

申请号：US10946000

申请日：2004-09-22

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06900492B2

公开(公告)日：2005-05-31

申请号：US10164008

申请日：2002-06-07

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/4941 ,  H01L29/6656

摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。 存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。 通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。 此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。 结果，可以以自对准的方式降低硼渗透并形成接触电极。 此外，可以提高构成逻辑电路的MISFET的性能。

公开(公告)号：US20050208716A1

公开(公告)日：2005-09-22

申请号：US11130236

申请日：2005-05-17

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/49

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/4941 ,  H01L29/6656

摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。 存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。 通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。 此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。 结果，可以以自对准的方式降低硼渗透并形成接触电极。 此外，可以提高构成逻辑电路的MISFET的性能。

公开(公告)号：US06809364B2

公开(公告)日：2004-10-26

申请号：US10630695

申请日：2003-07-31

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

公开(公告)号：US06621110B1

公开(公告)日：2003-09-16

申请号：US09592648

申请日：2000-06-13

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

摘要翻译： 开放位线结构的DRAM具有小于折叠位线结构的DRAM的单元面积，并且易受噪声影响。 开放位线结构的常规DRAM具有大的位线电容，并且易于噪声或具有大的单元面积。 已经没有开放位线结构的DRAM具有小的位线电容，不能被噪声感知并且具有小的单元面积。 本发明形成与位线不对齐的电容器下电极插孔，以减少位线电容。 位线形成为小的宽度，电容器下电极插头从与位线相对应的位置的位置脱位，并且触点形成为减小的直径，以避免增加电池面积。 因此，提供了耐噪声且具有小单元面积的开放位线结构的半导体存储装置。

公开(公告)号：US20060274593A1

公开(公告)日：2006-12-07

申请号：US11501118

申请日：2006-08-09

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

IPC分类号： G11C17/18

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/76 ,  G11C2213/79

摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

公开(公告)号：US07123535B2

公开(公告)日：2006-10-17

申请号：US11002245

申请日：2004-12-03

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Riichiro Takemura

IPC分类号： G11C17/18

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/76 ,  G11C2213/79

摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

公开(公告)号：US07098478B2

公开(公告)日：2006-08-29

申请号：US11168872

申请日：2005-06-29

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US06670642B2

公开(公告)日：2003-12-30

申请号：US10051188

申请日：2002-01-22

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.