发明申请
- 专利标题: Semiconductor device and manufacturing method of semiconductor device
- 专利标题(中): 半导体器件及半导体器件的制造方法
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申请号: US10991485申请日: 2004-11-19
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公开(公告)号: US20050093035A1公开(公告)日: 2005-05-05
- 发明人: Atsushi Yagishita , Tomohiro Saito
- 申请人: Atsushi Yagishita , Tomohiro Saito
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 优先权: JPP2002-95879 20020329
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/8234 ; H01L21/84 ; H01L27/08 ; H01L27/088 ; H01L27/12 ; H01L29/423 ; H01L29/49 ; H01L29/786 ; H01L29/04 ; H01L31/036
摘要:
Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate, grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.