公开(公告)号：US20120049281A1

公开(公告)日：2012-03-01

申请号：US12870011

申请日：2010-08-27

申请人： Yoshinori Tsuchiya ,  Ryosuke Iijima ,  Atsushi Yagishita

发明人： Yoshinori Tsuchiya ,  Ryosuke Iijima ,  Atsushi Yagishita

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： According to one embodiment, gate electrodes of a multi-gate field effect transistors and methods of making a gate electrode of a multi-gate field effect transistor are provided. The gate electrode can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The gate electrode does not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin. In another embodiment, the gate electrode can contain an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer.

摘要翻译： 根据一个实施例，提供了多栅极场效应晶体管的栅极和制造多栅极场效应晶体管的栅电极的方法。 栅电极可以包含半导体衬底; 半导体衬底上的电介质层; 电介质层上的翅片; 在翅片的侧表面上的栅极绝缘层; 翅片上的栅极电极层; 和鳍上的多晶硅层。 栅电极除电介质层上表面的与栅极侧表面上形成的栅极绝缘层的侧面接触的部分以外，在电介质层的上表面上不包含栅极绝缘层。 在另一个实施例中，栅电极可以在电介质层的上表面上包含氧扩散阻挡层或第一氧扩散层。

公开(公告)号：US08053292B2

公开(公告)日：2011-11-08

申请号：US12805533

申请日：2010-08-04

申请人： Akio Kaneko ,  Atsushi Yagishita ,  Satoshi Inaba

发明人： Akio Kaneko ,  Atsushi Yagishita ,  Satoshi Inaba

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/6681 ,  H01L29/7843

摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

摘要翻译： 本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力， 在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

公开(公告)号：US07723171B2

公开(公告)日：2010-05-25

申请号：US12078585

申请日：2008-04-02

申请人： Atsushi Yagishita ,  Akio Kaneko ,  Kazunari Ishimaru

发明人： Atsushi Yagishita ,  Akio Kaneko ,  Kazunari Ishimaru

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/28097 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising:depositing a mask material on a semiconductor substrate;patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region;burying a device isolation insulating film in the trench;etching away a predetermined amount of the device isolation insulating film formed in the first region;etching away the mask material formed in the second region;forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection;depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film;planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region;depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; andpatterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.

摘要翻译： 根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

公开(公告)号：US20100081240A1

公开(公告)日：2010-04-01

申请号：US12585554

申请日：2009-09-17

申请人： Atsushi Yagishita

发明人： Atsushi Yagishita

IPC分类号： H01L21/86

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.

摘要翻译： 制造半导体器件的方法包括在绝缘层上形成包括半导体材料的多个金属丝; 在金属丝的侧壁上形成栅极绝缘膜; 形成栅极电极，所述栅电极在所述鳍片的布置方向上延伸并且与所述鳍状物电绝缘，所述栅极电极在所述栅极绝缘膜上的所述鳍片中是共同的; 通过使用栅极电极作为掩模将杂质注入到薄片的部分中以形成源极 - 漏极扩散层，鳍状物的部分在栅电极的两侧延伸; 以及在所述金属丝的两侧上沉积导电材料以将所述金属丝彼此连接。

公开(公告)号：US07537978B2

公开(公告)日：2009-05-26

申请号：US11717068

申请日：2007-03-13

申请人： Atsushi Yagishita ,  Ichiro Mizushima ,  Tsutomu Sato

发明人： Atsushi Yagishita ,  Ichiro Mizushima ,  Tsutomu Sato

IPC分类号： H01L21/00

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/78639 ,  H01L29/78648

摘要： A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.

摘要翻译： 半导体器件包括由半导体制成的支撑层，通过在支撑层的表面层中注入杂质形成的扩散层，设置在扩散层上的掩埋绝缘层，设置在掩埋绝缘层上的岛状有源层， 形成在有源层中的沟道区域，形成在有源层中的源极和漏极区域，夹持沟道区域，形成在沟道区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极和岛的侧表面 类型的有源层，并且与沟道，源极和漏极区域绝缘和隔离，以及连接到有源层的电极。

公开(公告)号：US20070099385A1

公开(公告)日：2007-05-03

申请号：US11540708

申请日：2006-10-02

申请人： Kazuaki Nakajima ,  Atsushi Yagishita

发明人： Kazuaki Nakajima ,  Atsushi Yagishita

IPC分类号： H01L21/336

CPC分类号： H01L21/823835 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of manufacturing a semiconductor device, comprising forming an electrode pattern made of silicon on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate, masking the n-MOS region including the first electrode pattern with a first insulating film pattern, forming a first metal film made of platinum all over the surface, forming a gate electrode consisting of a platinum silicide in the p-MOS region, forming an silicon oxide film on the surface of the gate electrode by oxidation, dissolving away a non-reacting Pt film, removing the first insulating film pattern, masking the p-MOS region including the electrode pattern with a second insulating film pattern, forming a second metal film made of europium all over the surface, and forming a gate electrode consisting of a europium silicide in the n-MOS region.

摘要翻译： 本发明提供一种制造半导体器件的方法，包括在n-MOS区的栅极绝缘膜和半导体衬底的p-MOS区中形成由硅制成的电极图案，掩蔽包括 具有第一绝缘膜图案的第一电极图案，在整个表面上形成由铂制成的第一金属膜，在p-MOS区中形成由铂硅化物组成的栅电极，在栅极的表面上形成氧化硅膜 电极通过氧化，去除不反应的Pt膜，去除第一绝缘膜图案，用第二绝缘膜图案掩蔽包括电极图案的p-MOS区，在整个表面上形成由铕制成的第二金属膜， 以及在n-MOS区中形成由硅化铕构成的栅电极。

公开(公告)号：US06815279B2

公开(公告)日：2004-11-09

申请号：US09907952

申请日：2001-07-19

申请人： Atsushi Yagishita ,  Kouji Matsuo

发明人： Atsushi Yagishita ,  Kouji Matsuo

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1054

摘要： A semiconductor device in which an NMOSFET and a PMOSFET are formed in a silicon substrate, wherein the gate electrodes of NMOSFET and PMOSFET are made of metallic materials, an Si—Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.

公开(公告)号：US06515338B1

公开(公告)日：2003-02-04

申请号：US09533765

申请日：2000-03-23

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  Y10S257/90

摘要： A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一膜和第二膜，选择性地去除第二膜，第一膜和半导体衬底的顶部以形成第一槽，将第一绝缘体 在第一凹槽中形成隔离区域，对由隔离区域包围的第二膜进行构图以形成伪栅极层，使用伪栅极层作为掩模将杂质掺杂到半导体衬底上，在第二绝缘膜上形成第二绝缘膜 由虚拟栅极层和第一绝缘膜包围的半导体衬底，去除伪栅极层和第一膜以形成第二沟槽，在第二沟槽中的半导体衬底上形成栅极绝缘膜，并在栅极电极上形成栅电极 栅极绝缘膜在第二凹槽中。

公开(公告)号：US6087698A

公开(公告)日：2000-07-11

申请号：US828289

申请日：1997-03-21

申请人： Tomohiro Saito ,  Minoru Takahashi ,  Atsushi Yagishita

发明人： Tomohiro Saito ,  Minoru Takahashi ,  Atsushi Yagishita

IPC分类号： H01L27/08 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L31/0376 ,  H01L27/01 ,  H01L29/76 ,  H01L31/036

CPC分类号： H01L29/66772 ,  H01L21/28123 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/78675

摘要： A semiconductor device includes an underlying layer formed by a first insulation layer, a plurality of island semiconductor layers formed on the first insulation layer, source and drain regions formed in each of the island semiconductor layers, a first gate electrode formed between the source and drain regions and formed on and insulated from the island semiconductor layer, a second insulation layer formed on the sides of the island semiconductor layer and along the periphery of the first gate electrode, the second insulation layer being higher than the surface of the island semiconductor layer and lower than the surface of the first gate electrode, and a second gate electrode formed over both the first gate electrode and the second insulation layer.

摘要翻译： 半导体器件包括由第一绝缘层形成的下层，形成在第一绝缘层上的多个岛状半导体层，形成在每个岛状半导体层中的源极和漏极区域，形成在源极和漏极之间的第一栅电极 区域，形成在岛状半导体层上并与岛半导体层绝缘;第二绝缘层，形成在岛状半导体层的侧面上并且沿着第一栅电极的周边，第二绝缘层高于岛状半导体层的表面， 低于第一栅电极的表面，以及形成在第一栅电极和第二绝缘层两者上的第二栅电极。

公开(公告)号：US5872383A

公开(公告)日：1999-02-16

申请号：US880695

申请日：1997-06-23

申请人： Atsushi Yagishita

发明人： Atsushi Yagishita

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/336 ,  H01L21/84 ,  H01L27/08 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/785

摘要： Disclosed is a semiconductor device, comprising a substrate having a first region and a second region surrounding the first region, a MOS transistor formed in the first region, a first conductive layer formed in the first region and constituting the lower layer of a two-layered gate electrode of the MOS transistor, a second conductive layer for isolation, the second conductive layer being formed in the second region and having an upper surface whose level is lower than that of the upper surface of the first conductive layer, a first insulating layer formed between the first and second regions, a second insulating layer formed on the second conductive layer, and a third conductive layer formed over the first conductive layer and the second insulating layer and constituting the upper layer of the two-layered gate electrode of the MOS transistor.

摘要翻译： 公开了一种半导体器件，包括具有第一区域和围绕第一区域的第二区域的衬底，形成在第一区域中的MOS晶体管，形成在第一区域中并构成第二区域的下层的第一导电层 MOS晶体管的栅电极，用于隔离的第二导电层，所述第二导电层形成在所述第二区域中，并且具有比所述第一导电层的上表面的上表面低的上表面，形成第一绝缘层 在第一和第二区域之间，形成在第二导电层上的第二绝缘层和形成在第一导电层和第二绝缘层上并构成MOS晶体管的双层栅电极的上层的第三导电层 。