公开(公告)号：US07915130B2

公开(公告)日：2011-03-29

申请号：US12588336

申请日：2009-10-13

申请人： Tomohiro Saito ,  Akio Kaneko ,  Atsushi Yagishita

发明人： Tomohiro Saito ,  Akio Kaneko ,  Atsushi Yagishita

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/4908 ,  H01L29/785

摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.

摘要翻译： 本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

公开(公告)号：US07242064B2

公开(公告)日：2007-07-10

申请号：US10810837

申请日：2004-03-29

申请人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

发明人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/78609

摘要： In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

摘要翻译： 在半导体器件中，形成在半导体衬底上的MISFET的栅极电连接到MISFET的沟道下方的阱区，MISFET形成在形成在半导体衬底上的岛状元件区域中，并且电气 MISFET的栅电极和半导体衬底中的阱区之间的连接在岛状元件区域的侧表面上进行。

公开(公告)号：US20070148843A1

公开(公告)日：2007-06-28

申请号：US11635039

申请日：2006-12-07

申请人： Tomohiro Saito ,  Akio Kaneko ,  Atsushi Yagishita

发明人： Tomohiro Saito ,  Akio Kaneko ,  Atsushi Yagishita

IPC分类号： H01L21/8242 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/4908 ,  H01L29/785

摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.

摘要翻译： 本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

公开(公告)号：US20050093035A1

公开(公告)日：2005-05-05

申请号：US10991485

申请日：2004-11-19

申请人： Atsushi Yagishita ,  Tomohiro Saito

发明人： Atsushi Yagishita ,  Tomohiro Saito

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate, grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.

摘要翻译： 在SOI衬底的硅有源层103上形成虚拟栅极图案111,112，然后去除这些虚拟栅极图案111,112以形成栅极沟槽130,132。通过蚀刻栅极图案111,112来调节每个晶体管的阈值电压 这些栅极，沟槽130,132中的任一个中的硅有源层103，以减小构成沟道区域的部分的厚度。 这样可以根据条件提高电路设计中的自由度等。

公开(公告)号：US06794720B2

公开(公告)日：2004-09-21

申请号：US10200445

申请日：2002-07-23

申请人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

发明人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

IPC分类号： H01L2712

CPC分类号： H01L29/7853 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66795 ,  H01L29/78609 ,  Y10S257/901

摘要： In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

摘要翻译： 在半导体器件中，形成在半导体衬底上的MISFET的栅极电连接到MISFET的沟道下方的阱区，MISFET形成在形成在半导体衬底上的岛状元件区域中，并且电气 MISFET的栅电极和半导体衬底中的阱区之间的连接在岛状元件区域的侧表面上进行。

公开(公告)号：US07479423B2

公开(公告)日：2009-01-20

申请号：US11709270

申请日：2007-02-22

申请人： Atsushi Yagishita ,  Tomohiro Saito

发明人： Atsushi Yagishita ,  Tomohiro Saito

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.

摘要翻译： 在SOI衬底的硅有源层103上形成虚拟栅极图案111,112，然后去除这些虚拟栅极图案111,112以形成栅极沟槽130,132。通过蚀刻栅极图案111,112来调节每个晶体管的阈值电压 这些栅极沟槽130,132中的任何一个中的硅有源层103，以减小构成沟道区域的部分的厚度。 这样可以根据条件提高电路设计中的自由度等。

公开(公告)号：US06465823B1

公开(公告)日：2002-10-15

申请号：US09609713

申请日：2000-06-30

申请人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

发明人： Atsushi Yagishita ,  Tomohiro Saito ,  Toshihiko Iinuma

IPC分类号： H01L21336

CPC分类号： H01L29/7853 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66795 ,  H01L29/78609 ,  Y10S257/901

摘要： In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

摘要翻译： 在半导体器件中，形成在半导体衬底上的MISFET的栅极电连接到MISFET的沟道下方的阱区，MISFET形成在形成在半导体衬底上的岛状元件区域中，并且电气 MISFET的栅电极和半导体衬底中的阱区之间的连接在岛状元件区域的侧表面上进行。

公开(公告)号：US06515338B1

公开(公告)日：2003-02-04

申请号：US09533765

申请日：2000-03-23

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  Y10S257/90

摘要： A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一膜和第二膜，选择性地去除第二膜，第一膜和半导体衬底的顶部以形成第一槽，将第一绝缘体 在第一凹槽中形成隔离区域，对由隔离区域包围的第二膜进行构图以形成伪栅极层，使用伪栅极层作为掩模将杂质掺杂到半导体衬底上，在第二绝缘膜上形成第二绝缘膜 由虚拟栅极层和第一绝缘膜包围的半导体衬底，去除伪栅极层和第一膜以形成第二沟槽，在第二沟槽中的半导体衬底上形成栅极绝缘膜，并在栅极电极上形成栅电极 栅极绝缘膜在第二凹槽中。

公开(公告)号：US6087698A

公开(公告)日：2000-07-11

申请号：US828289

申请日：1997-03-21

申请人： Tomohiro Saito ,  Minoru Takahashi ,  Atsushi Yagishita

发明人： Tomohiro Saito ,  Minoru Takahashi ,  Atsushi Yagishita

IPC分类号： H01L27/08 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L31/0376 ,  H01L27/01 ,  H01L29/76 ,  H01L31/036

CPC分类号： H01L29/66772 ,  H01L21/28123 ,  H01L21/84 ,  H01L29/42384 ,  H01L29/78675

摘要： A semiconductor device includes an underlying layer formed by a first insulation layer, a plurality of island semiconductor layers formed on the first insulation layer, source and drain regions formed in each of the island semiconductor layers, a first gate electrode formed between the source and drain regions and formed on and insulated from the island semiconductor layer, a second insulation layer formed on the sides of the island semiconductor layer and along the periphery of the first gate electrode, the second insulation layer being higher than the surface of the island semiconductor layer and lower than the surface of the first gate electrode, and a second gate electrode formed over both the first gate electrode and the second insulation layer.

摘要翻译： 半导体器件包括由第一绝缘层形成的下层，形成在第一绝缘层上的多个岛状半导体层，形成在每个岛状半导体层中的源极和漏极区域，形成在源极和漏极之间的第一栅电极 区域，形成在岛状半导体层上并与岛半导体层绝缘;第二绝缘层，形成在岛状半导体层的侧面上并且沿着第一栅电极的周边，第二绝缘层高于岛状半导体层的表面， 低于第一栅电极的表面，以及形成在第一栅电极和第二绝缘层两者上的第二栅电极。

公开(公告)号：US20070148937A1

公开(公告)日：2007-06-28

申请号：US11709270

申请日：2007-02-22

申请人： Atsushi Yagishita ,  Tomohiro Saito

发明人： Atsushi Yagishita ,  Tomohiro Saito

IPC分类号： H01L21/00 ,  H01L21/3205

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Dummy gate patterns 111, 112 are formed on a silicon active layer 103 of an SOI substrate, and thereafter, these dummy gate patterns 111, 112 are removed to form gate grooves 130, 132. A threshold voltage of each transistor is adjusted by etching a silicon active layer 103 in any one of these gate grooves 130, 132 to reduce a thickness of a portion constituting a channel region. This enables the enhancement of freedom degree and so on in circuit designing according to conditions.

摘要翻译： 在SOI衬底的硅有源层103上形成虚拟栅极图案111,112，然后去除这些虚拟栅极图案111,112以形成栅极沟槽130,132。通过蚀刻栅极图案111,112来调节每个晶体管的阈值电压 这些栅极沟槽130,132中的任何一个中的硅有源层103，以减小构成沟道区域的部分的厚度。 这样可以根据条件提高电路设计中的自由度等。