发明申请
- 专利标题: Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device
- 专利标题(中): 半导体集成电路器件和半导体集成电路器件的制造方法
-
申请号: US11055745申请日: 2005-02-11
-
公开(公告)号: US20050148155A1公开(公告)日: 2005-07-07
- 发明人: Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
- 申请人: Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
- 优先权: JP2000-012026 20000120
- 主分类号: H01L21/76
- IPC分类号: H01L21/76 ; G02B17/00 ; G02B21/00 ; G02B23/00 ; H01L21/302 ; H01L21/312 ; H01L21/316 ; H01L21/461 ; H01L21/762 ; H01L21/8239 ; H01L21/8242 ; H01L27/02 ; H01L27/10 ; H01L27/105 ; H01L27/108
摘要:
A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited
公开/授权文献
信息查询
IPC分类: