摘要:
A method of forming a feature in a void, the method including filling the void having at least one sloped wall with a polymeric material; forming a layer of photoresist over the polymeric material; forming a gap in the layer of photoresist; and etching the polymeric material exposed by the gap in the layer of photoresist to form a feature.
摘要:
A silicone structure-bearing polymer comprising recurring units derived from a bis(4-hydroxy-3-allylphenyl) derivative and having a Mw of 3,000-500,000 is provided. A chemically amplified negative resist composition comprising the polymer overcomes the stripping problem that a coating is stripped from metal wirings of Cu or Al, electrodes, and SiN substrates.
摘要:
Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound, e.g., an acid or a base, to at least a lower surface of a resist to alter acidity of at least a segment of one of an exposed, acidic resist region and an unexposed, basic resist region. The alteration, e.g., increase or decrease, in the acidity shifts an acid-base equilibrium to either encourage or discourage development of the segment. Such “chemical proximity correction” techniques may be used to enhance the acidity of an exposed, acidic resist segment, to enhance the basicity of an unexposed, basic resist segment, or to effectively convert an exposed, acidic resist segment to an unexposed, basic resist segment or vice versa. Thus, unwanted line breaks, line merges, or misalignments may be avoided.
摘要:
A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
摘要:
According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.
摘要:
An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process.
摘要:
A fabricating method and apparatus of a thin film pattern improves the reliability of forming the thin film pattern by a resist printing method. The apparatus includes a print roller device of a roll shape around which a blanket is wound; a spray device located around the print roller device for spraying an etch resist solution to the blanket; and a print plate of an engraved shape where a groove of a desired thin film shape and a projected part except the groove are formed, and the etch resist solution has a surfactant inclusive of an ethylene oxide fluorinated polymer material.
摘要:
To provide a gate insulating material which has high chemical resistance, is superior in coatability of a resist and an organic semiconductor coating liquid, and has small hysteresis, a gate insulating film and an FET using the same by a polysiloxane having an epoxy group-containing silane compound as a copolymerization component.A gate insulating material containing a polysiloxane having, as copolymerization components, at least a silane compound represented by the general formula (1): R1mSi(OR2)4-m (1), wherein R1 represents hydrogen, an alkyl group, a cycloalkyl group, a heterocyclic group, an aryl group, a heteroaryl group or an alkenyl group and in the case where a plurality of R1s are present, R1s may be the same or different, R2 represents an alkyl group or a cycloalkyl group and in the case where a plurality of R2s are present, R2s may be the same or different, and m represents an integer of 1 to 3, and an epoxy group-containing silane compound represented by the general formula (2): R3nR4lSi(OR5)4-n-1 (2), wherein R3 represents an alkyl group or a cycloalkyl group having one or more epoxy groups in a part of a chain and in the case where a plurality of R3s are present, R3s may be the same or different, R4 represents hydrogen, an alkyl group, a cycloalkyl group, a heterocyclic group, an aryl group, a heteroaryl group or an alkenyl group and in the case where a plurality of R4s are present, R4s may be the same or different, R5 represents an alkyl group or a cycloalkyl group and in the case where a plurality of R5s are present, R5s may be the same or different, l represents an integer of 0 to 2, and n represents 1 or 2 (however, l+n≦3).
摘要:
Methods and systems for backside dielectric patterning for wafer warpage and stress control are disclosed and may include thinning a semiconductor wafer comprising one or more through silicon vias (TSVs) and one or more die to expose the TSVs on a first surface of the wafer. The wafer may be passivated by depositing dielectric layers. The passivated wafer may be planarized and portions dielectric layers may be selectively removed to reduce a strain on the wafer. Metal contacts may be placed on the exposed TSVs prior to or after the selectively removal. The die may comprise functional electronic die or interposer die. Portions of the dielectric layers may be selectively removed in a radial pattern and may comprise a nitride and/or silicon dioxide layer. The wafer may be thinned to below a top surface of the TSVs. The dielectric layers may be selectively removed utilizing a dry etch process.
摘要:
One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.