发明申请
US20050208748A1 METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING
有权
通过减少种植层不利影响形成稳定的焊接器互连结构的方法
- 专利标题： METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING
- 专利标题（中）： 通过减少种植层不利影响形成稳定的焊接器互连结构的方法
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申请号： US10708649申请日： 2004-03-17
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公开(公告)号： US20050208748A1公开(公告)日： 2005-09-22
- 发明人: Kamalesh Srivastava , Subhash Shinde , Tien-Jen Cheng , Sarah Knickerbocker , Roger Quon , William Sablinski , Julie Biggs , David Eichstadt , Jonathan Griffith
- 申请人： Kamalesh Srivastava , Subhash Shinde , Tien-Jen Cheng , Sarah Knickerbocker , Roger Quon , William Sablinski , Julie Biggs , David Eichstadt , Jonathan Griffith
- 申请人地址： US NY ARMONK
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY ARMONK
- 主分类号： H01L21/48
- IPC分类号： H01L21/48 ; H01L23/485
摘要：
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.
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