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    METHOD AND STRUCTURE FOR OPTIMIZING YIELD OF 3-D CHIP MANUFACTURE
    1.
    发明申请
    METHOD AND STRUCTURE FOR OPTIMIZING YIELD OF 3-D CHIP MANUFACTURE 有权
    3-D芯片制造优化的方法与结构

    公开(公告)号：US20070080448A1

    公开(公告)日：2007-04-12

    申请号：US11163226

    申请日：2005-10-11

    Applicant: Edward DeMulder ,  Sarah Knickerbocker ,  Michael Shapiro ,  Albert Young

    Inventor： Edward DeMulder ,  Sarah Knickerbocker ,  Michael Shapiro ,  Albert Young

    IPC: H01L23/488 ,  H01L21/58

    CPC classification number: H01L21/8221 ,  H01L27/0688 ,  H01L2224/13

    Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

    Abstract translation: 该过程开始于具有互补芯片的单独的器件晶片。 薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。 处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。 捕获垫被去除并在变薄后更换。 切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。 具有已知良好3-D芯片的器件晶片然后进行最终处理。

    Method of producing heat dissipating structure for semiconductor devices
    3.
    发明授权
    Method of producing heat dissipating structure for semiconductor devices 失效
    制造半导体器件散热结构的方法

    公开(公告)号：US06284574B1

    公开(公告)日：2001-09-04

    申请号：US09223979

    申请日：1999-01-04

    Applicant: Kevin Shawn Petrarca ,  Sarah Knickerbocker ,  Joyce C. Liu ,  Rebecca D. Mih

    Inventor： Kevin Shawn Petrarca ,  Sarah Knickerbocker ,  Joyce C. Liu ,  Rebecca D. Mih

    IPC: H01L2148

    CPC classification number: H01L23/36 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

    Abstract: A structure and process are described for facilitating the conduction of heat away from a semiconductor device. Thermally conductive planes and columns are incorporated within the back-end structure and around the interconnect outside the chip. A thermally conductive plane is formed by forming a first insulating layer on an underlying layer of the device; forming a recess in the insulating layer; filling the recess with a thermally conductive material to form a lateral heat-dissipating layer; planarizing the heat-dissipating layer to make the top surface thereof coplanar with the unrecessed portion of the insulating layer; and forming a second insulating layer on the first insulating layer and the heat-dissipating layer, thereby embedding the heat-dissipating layer between the first and second insulating layers. The heat-dissipating layer is electrically isolated from the underlying layer of the device, and preferably is electrically grounded.

    Abstract translation: 描述了用于促进远离半导体器件的热传导的结构和工艺。 导热平面和列结合在后端结构中并且围绕芯片外的互连。 导热平面通过在器件的下层上形成第一绝缘层而形成; 在所述绝缘层中形成凹部; 用导热材料填充凹部以形成横向散热层; 使散热层平坦化，使其顶面与绝缘层的未加工部分共面; 以及在所述第一绝缘层和所述散热层上形成第二绝缘层，从而将所述散热层嵌入所述第一绝缘层和所述第二绝缘层之间。 散热层与器件的下层电隔离，优选电接地。

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