发明申请
- 专利标题: Self-aligned isolation double-gate get
- 专利标题(中): 自对准隔离双门获得
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申请号: US11146624申请日: 2005-06-07
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公开(公告)号: US20050263797A1公开(公告)日: 2005-12-01
- 发明人: Kevin Chan , Guy Cohen , Meikei Ieong , Ronnen Roy , Paul Solomon , Min Yang
- 申请人: Kevin Chan , Guy Cohen , Meikei Ieong , Ronnen Roy , Paul Solomon , Min Yang
- 申请人地址: US NY ARMONK
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY ARMONK
- 主分类号: H01L29/417
- IPC分类号: H01L29/417 ; H01L21/02 ; H01L21/265 ; H01L21/336 ; H01L21/76 ; H01L21/762 ; H01L27/12 ; H01L29/423 ; H01L29/49 ; H01L29/78 ; H01L29/786 ; H01L21/4763 ; H01L21/8234 ; H01L27/148 ; H01L29/76 ; H01L29/768 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
摘要:
A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
公开/授权文献
- US07259049B2 Self-aligned isolation double-gate FET 公开/授权日:2007-08-21
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