发明申请
US20060145332A1 Semiconductor devices having post passivation interconnections with a second connection pattern 有权
具有具有第二连接图案的后钝化互连的半导体器件

Semiconductor devices having post passivation interconnections with a second connection pattern
摘要:
An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.
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