- 专利标题: Semiconductor memory device
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申请号: US11375060申请日: 2006-03-15
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公开(公告)号: US20060158918A1公开(公告)日: 2006-07-20
- 发明人: Hiroki Ueno , Takashi Akioka , Kinya Mitsumoto , Akihisa Aoyama , Masao Shinozaki
- 申请人: Hiroki Ueno , Takashi Akioka , Kinya Mitsumoto , Akihisa Aoyama , Masao Shinozaki
- 专利权人: Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人: Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 优先权: JP2000-386087 20001219
- 主分类号: G11C5/06
- IPC分类号: G11C5/06
摘要:
Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
公开/授权文献
- US07254068B2 Semiconductor memory device 公开/授权日:2007-08-07
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