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公开(公告)号：US07254068B2
公开(公告)日：2007-08-07
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的截面的中心位于这些 互补位线是一个等腰三角形。
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公开(公告)号：US20050128839A1
公开(公告)日：2005-06-16
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US06856559B2
公开(公告)日：2005-02-15
申请号：US10637549
申请日：2003-08-11
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的部分的直线布置在其上方 互补位线是一个等腰三角形。
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公开(公告)号：US06625070B2
公开(公告)日：2003-09-23
申请号：US10011488
申请日：2001-12-11
IPC分类号： G11C700
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US07068551B2
公开(公告)日：2006-06-27
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US20060158918A1
公开(公告)日：2006-07-20
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US07584604B2
公开(公告)日：2009-09-08
申请号：US10572545
申请日：2004-09-02
申请人： Nobuhiko Masaki , Kiminobu Hirata , Hiroki Ueno
发明人： Nobuhiko Masaki , Kiminobu Hirata , Hiroki Ueno
IPC分类号： F01N3/00
CPC分类号： F01N3/2066 , B01F3/04049 , B01F5/045 , B01F5/0466 , F01N2610/1453 , Y02T10/24
摘要： For preventing clogging in an injection nozzle for supplying a reducing agent to exhaust gas flow on an upstream side of a reducing catalyst and for improving the efficiency of NOx purification processing, the injection nozzle 14 has a tip end portion 18 provided with a ring shaped protruding ridge 19 disposed on an outer peripheral surface of an exhaust gas downstream side end portion of the tip end portion 18 that is arranged substantially in parallel with an exhaust gas flow direction A inside an exhaust pipe 13, the ring shaped protruding ridge 19 being provided with injection hole or holes 20 drilled outward from the central axis of the injection nozzle 14, so that the reducing agent is ejected on the exhaust gas upstream side of the reduction catalyst, from the injection holes 20. The injection holes 20 do not directly open on a wide outer peripheral surface of the injection nozzle 14, and then when injection stops, the reducing agent does not become attached to or does not remain around the injection holes 20, or the remaining amount thereof becomes small, so that clogging of the injection holes 20 of the injection nozzle 14 is prevented, and the efficiency of NOx purification processing is improved.
摘要翻译： 为了防止用于向还原催化剂的上游侧的废气流供给还原剂的喷嘴中的堵塞，并且为了提高NOx净化处理的效率，喷嘴14具有前端部18，其具有环状的突出部 脊部19配置在前端部18的排气下游侧端部的外周面上，该排气管下游侧端部与排气管13内的排气流动方向A大致平行地配置，环状突脊19设置有 从注射喷嘴14的中心轴线向外钻出的喷射孔或孔20，使得还原剂从喷射孔20喷射到还原催化剂的废气上游侧。喷射孔20不直接打开 注射喷嘴14的宽外周面，然后当注射停止时，还原剂不会附着或不附着 n，或者其剩余量变小，从而防止喷嘴14的喷射孔20的堵塞，并且提高NOx净化处理的效率。
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公开(公告)号：US20070101700A1
公开(公告)日：2007-05-10
申请号：US10572545
申请日：2004-09-02
申请人： Nobuhiko Masaki , Kiminobu Hirata , Hiroki Ueno
发明人： Nobuhiko Masaki , Kiminobu Hirata , Hiroki Ueno
CPC分类号： F01N3/2066 , B01F3/04049 , B01F5/045 , B01F5/0466 , F01N2610/1453 , Y02T10/24
摘要： For preventing clogging in an injection nozzle for supplying a reducing agent to exhaust gas flow on an upstream side of a reducing catalyst and for improving the efficiency of NOx purification processing, the injection nozzle 14 has a tip end portion 18 provided with a ring shaped protruding ridge 19 disposed on an outer peripheral surface of an exhaust gas downstream side end portion of the tip end portion 18 that is arranged substantially in parallel with an exhaust gas flow direction A inside an exhaust pipe 13, the ring shaped protruding ridge 19 being provided with injection hole or holes 20 drilled outward from the central axis of the injection nozzle 14, so that the reducing agent is ejected on the exhaust gas upstream side of the reduction catalyst, from the injection holes 20. The injection holes 20 do not directly open on a wide outer peripheral surface of the injection nozzle 14, and then when injection stops, the reducing agent does not become attached to or does not remain around the injection holes 20, or the remaining amount thereof becomes small, so that clogging of the injection holes 20 of the injection nozzle 14 is prevented, and the efficiency of NOx purification processing is improved.
摘要翻译： 为了防止用于向还原催化剂的上游侧的废气流供给还原剂的喷嘴中的堵塞，并且为了提高NOx净化处理的效率，喷嘴14具有前端部18，其具有环状的突出部 脊部19配置在前端部18的排气下游侧端部的外周面上，该排气管下游侧端部与排气管13内的排气流动方向A大致平行地配置，环状突脊19设置有 从注射喷嘴14的中心轴线向外钻出的喷射孔或孔20，使得还原剂从喷射孔20喷射到还原催化剂的废气上游侧。喷射孔20不直接打开 注射喷嘴14的宽外周面，然后当注射停止时，还原剂不会附着或不附着 n，或者其剩余量变小，从而防止喷嘴14的喷射孔20的堵塞，并且提高NOx净化处理的效率。
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公开(公告)号：US20050110516A1
公开(公告)日：2005-05-26
申请号：US10968945
申请日：2004-10-21
申请人： Hiroki Ueno
发明人： Hiroki Ueno
IPC分类号： G11C11/417 , H01L21/822 , H01L27/04 , H03K19/00 , H03K19/0175 , H03K19/0948 , H03K19/003
CPC分类号： H03K19/0005
摘要： The present invention provides a semiconductor device that can shorten the initialization cycle of impedance matching of interface buffers and reduce as much as possible affects on other circuits at the time of fine control thereafter. The semiconductor device (1) includes interface buffers (18a to 18c) whose internal impedances are controlled by impedance control data and an impedance control circuit (35) that generates the impedance control data. The impedance control circuit includes a first impedance control mode that initially generates the impedance control data by a binary search and comparison operation resulting from predetermined impedance control steps and sets the impedance control data in the interface buffers, and a second impedance control mode that updates the impedance control data set in the interface buffers by a sequential comparison operation resulting from the predetermined impedance control steps.
摘要翻译： 本发明提供一种半导体器件，其可以缩短接口缓冲器的阻抗匹配的初始化周期，并且在此后精细控制时尽可能地减少对其他电路的影响。 半导体器件（1）包括内部阻抗由阻抗控制数据控制的接口缓冲器（18a至18c）和产生阻抗控制数据的阻抗控制电路（35）。 阻抗控制电路包括第一阻抗控制模式，其通过由预定的阻抗控制步骤产生的二进制搜索和比较操作来产生阻抗控制数据，并设置接口缓冲器中的阻抗控制数据，以及第二阻抗控制模式， 通过由预定阻抗控制步骤产生的顺序比较操作在接口缓冲器中设置的阻抗控制数据。
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公开(公告)号：US07849674B2
公开(公告)日：2010-12-14
申请号：US10572558
申请日：2004-09-02
申请人： Kouji Masuda , Kiminobu Hirata , Hisashi Akagawa , Shuichi Nakamura , Hiroki Ueno , Ikuo Sakai
发明人： Kouji Masuda , Kiminobu Hirata , Hisashi Akagawa , Shuichi Nakamura , Hiroki Ueno , Ikuo Sakai
IPC分类号： F01N3/00
CPC分类号： F01N3/208 , B01D53/9409 , B01D2251/2062 , F01N3/105 , F01N3/106 , F01N3/206 , F01N11/002 , F01N13/009 , F01N13/0097 , F01N2610/02 , F01N2610/08 , F01N2610/10 , F01N2610/1406 , F01N2610/1486 , Y02T10/24 , Y02T10/47
摘要： A NOx reduction catalyst and an ammonia slip oxidation catalyst are disposed in an exhaust system in this order, and also, an electric fan is disposed on piping which communicates an upper space of a storage tank storing therein a reducing agent with the exhaust upstream of the NOx reduction catalyst. Then, when the temperature of the ammonia slip oxidation catalyst reaches or exceeds the temperature for activating a catalyst thereof, the electric fan is operated for a predetermined period of time, so that the gas (ammonia series gas) in the upper space of the storage tank is forcibly discharged to the upstream side of the NOx reduction catalyst. Further, a discharge-forcing device, such as an electric fan or the like, forcibly discharging the gas in the upper space of the storage tank, an adsorbing device temporarily adsorbing thereto the forcibly discharged gas and an oxidation catalyst oxidizing the gas desorbed from the adsorbing device, may be disposed to the storage tank in this order.
摘要翻译： 在排气系统中依次配置NOx还原催化剂和氨滑移式氧化催化剂，并且还将电风扇设置在将储存有还原剂的储罐的上部空间连通到上游的排气管 NOx还原催化剂。 然后，当氨滑动氧化催化剂的温度达到或超过其催化剂的活化温度时，电风扇运转预定的时间，使得储存器的上部空间中的气体（氨气系列气体） 罐被强制排出到NOx还原催化剂的上游侧。 此外，诸如电动风扇等的放电装置强制地排出储罐上部空间中的气体，临时吸附到强制排出气体的吸附装置和氧化从所述储存罐解吸的气体的氧化催化剂 吸附装置可以按顺序设置在储罐上。
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