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34 条记录 (耗时 0.025 秒)

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07254068B2

    公开(公告)日：2007-08-07

    申请号：US11375060

    申请日：2006-03-15

    申请人： Hiroki Ueno ,  Takashi Akioka ,  Kinya Mitsumoto ,  Akihisa Aoyama ,  Masao Shinozaki

    发明人： Hiroki Ueno ,  Takashi Akioka ,  Kinya Mitsumoto ,  Akihisa Aoyama ,  Masao Shinozaki

    IPC分类号： G11C7/00

    CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

    摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

    摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的截面的中心位于这些 互补位线是一个等腰三角形。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06856559B2

    公开(公告)日：2005-02-15

    申请号：US10637549

    申请日：2003-08-11

    申请人： Hiroki Ueno ,  Takashi Akioka ,  Kinya Mitsumoto ,  Akihisa Aoyama ,  Masao Shinozaki

    发明人： Hiroki Ueno ,  Takashi Akioka ,  Kinya Mitsumoto ,  Akihisa Aoyama ,  Masao Shinozaki

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/18 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

    CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

    摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.

    摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的部分的直线布置在其上方 互补位线是一个等腰三角形。

    Semiconductor device and method of manufacturing a semiconductor device
    7.
    发明授权
    Semiconductor device and method of manufacturing a semiconductor device 失效
    半导体装置及其制造方法

    公开(公告)号：US06770941B2

    公开(公告)日：2004-08-03

    申请号：US10002009

    申请日：2001-12-05

    申请人： Masao Shinozaki ,  Takashi Akioka ,  Kinya Mitsumoto

    发明人： Masao Shinozaki ,  Takashi Akioka ,  Kinya Mitsumoto

    IPC分类号： H01L2976

    CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823462

    摘要： The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.

    摘要翻译： 本发明提供一种在不增加芯片尺寸和生产成本的情况下制造符合多种电源电压规格的半导体器件的方法，同时器件实现高速性能。 该方法包括多个处理，用于形成与外部电源电压相对应地供应不同电源电压的多种类型的MOS晶体管，这些外部电源电压由多种类型的MOS晶体管共同的第一种处理，第一种处理之后的第二种处理， 这是多种类型的MOS晶体管中的每一种不同的，以及第二种处理之后的第三种处理，这对于多种类型的MOS晶体管是共同的。