发明申请
US20070158835A1 Method for designing interconnect for a new processing technology
审中-公开
用于设计新加工技术的互连的方法
- 专利标题： Method for designing interconnect for a new processing technology
- 专利标题（中）： 用于设计新加工技术的互连的方法
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申请号： US11332566申请日： 2006-01-12
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公开(公告)号： US20070158835A1公开(公告)日： 2007-07-12
- 发明人: Jian-Hong Lin , Hsueh-Chung Chen , Yi-Lung Cheng , Ta-Wei Lee , Chih-Tao Lin , Jyh-Kang Ting , Lee-Chung Lu
- 申请人： Jian-Hong Lin , Hsueh-Chung Chen , Yi-Lung Cheng , Ta-Wei Lee , Chih-Tao Lin , Jyh-Kang Ting , Lee-Chung Lu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.
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