Invention Application
- Patent Title: Chip stack package
- Patent Title (中): 芯片堆栈封装
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Application No.: US11703900Application Date: 2006-12-19
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Publication No.: US20070200216A1Publication Date: 2007-08-30
- Inventor: Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
- Applicant: Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Priority: KR2004-45567 20040618
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.
Information query
IPC分类: