公开(公告)号：US08663388B2

公开(公告)日：2014-03-04

申请号：US12436754

申请日：2009-05-06

申请人： Se Young Jeong ,  Chae Ryong Cho ,  Sang Eon Park ,  Sung Kyu Kim

发明人： Se Young Jeong ,  Chae Ryong Cho ,  Sang Eon Park ,  Sung Kyu Kim

IPC分类号： C30B11/00

CPC分类号： C30B15/00 ,  C22B11/02 ,  C30B11/00 ,  C30B11/14 ,  C30B15/36 ,  C30B29/02 ,  C30B29/62

摘要： Disclosed are a single crystal wire and other single crystal articles, and a manufacturing method thereof. The method comprises the steps of: placing into a growth crucible at least one metal selected from the group consisting of gold, copper, silver, aluminum and nickel; heating and melting the metal placed in the growth crucible; growing a single crystal using metal crystal as a seed by Czochralski or Bridgman method; cutting the grown single crystal by electric discharge machining; and machining the cut single crystal and producing a wire or other articles such as a ring. In the method, the grown metal single crystal is cut into a disc-shaped piece by electric discharge machining. The piece is transformed into a single crystal wire or other articles by wire-cut electric discharge machining, and the single crystal wire can be used as a ring, a pendant, or a wire for high-quality cables for audio and video systems. Also, the single crystal formed into the disc-shaped piece by electric discharge machining can be used as a substrate and a target for deposition.

摘要翻译： 公开了单晶线及其它单晶制品及其制造方法。 该方法包括以下步骤：将生长坩埚放入至少一种选自金，铜，银，铝和镍的金属; 加热和熔化置于生长坩埚中的金属; 使用Czochralski或Bridgman方法生长使用金属晶体作为种子的单晶; 通过放电加工切割生长的单晶; 并加工切割的单晶并生产线或其它物品如环。 在该方法中，通过放电加工将成长的金属单晶切割成圆盘状的片。 该片通过线切割放电加工转换为单晶线或其他物品，单晶线可用作音频和视频系统的高品质电缆的环形，吊坠或线材。 此外，通过放电加工形成为盘状片的单晶可以用作基板和沉积靶。

公开(公告)号：US07732319B2

公开(公告)日：2010-06-08

申请号：US11875713

申请日：2007-10-19

申请人： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

发明人： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

摘要翻译： 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US07132358B2

公开(公告)日：2006-11-07

申请号：US10922172

申请日：2004-08-20

申请人： Se-Young Jeong ,  Jin-Hak Choi ,  Nam-Seog Kim ,  Kang-Wook Lee

发明人： Se-Young Jeong ,  Jin-Hak Choi ,  Nam-Seog Kim ,  Kang-Wook Lee

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  Y10S438/951 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer and covers the second UBM layer. A solder bump may be formed in the opening. The second photoresist pattern and the first photoresist pattern may be removed using a stripper, thereby removing the second UBM layer by a lift-off method.

摘要翻译： 形成焊料凸点的方法可以包括在具有焊盘的晶片上形成第一光致抗蚀剂图案。 第一光致抗蚀剂图案可以具有露出垫的一部分的开口。 可以在焊盘上形成第一凸点下冶金（UBM）层，并且可以在第一光致抗蚀剂图案上形成第二UBM层。 可以形成第二光致抗蚀剂图案，其暴露第一UBM层并覆盖第二UBM层。 可以在开口中形成焊料凸块。 可以使用剥离剂除去第二光致抗蚀剂图案和第一光致抗蚀剂图案，从而通过剥离方法去除第二UBM层。

公开(公告)号：US20060202332A1

公开(公告)日：2006-09-14

申请号：US11418010

申请日：2006-05-05

申请人： Se-Young Jeong ,  Gi-Young Sohn ,  Ki-Kwon Jeong ,  Hyeon Hwang

发明人： Se-Young Jeong ,  Gi-Young Sohn ,  Ki-Kwon Jeong ,  Hyeon Hwang

IPC分类号： H01L23/48

CPC分类号： H01L21/4835 ,  H01L23/49582 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/45099 ,  H01L2924/00

摘要： Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus includes a plating unit that is disposed in a direction to form a conductive plating layer on external terminals of the semiconductor chip package; and a reflow unit that is disposed with the plating unit to melt the conductive plating layer. The packaging apparatus may further include a rinsing unit that is disposed with the plating unit to clean and cool the conductive plating layer. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

摘要翻译： 公开了半导体芯片封装装置及其方法的示例性实施例。 包装装置包括镀敷单元，该镀覆单元沿着在半导体芯片封装的外部端子上形成导电镀层的方向设置; 以及与所述电镀单元配置以熔化所述导电性镀层的回流单元。 包装装置还可以包括与镀覆单元一起设置以清洁和冷却导电镀层的冲洗单元。 因此，可以有效地抑制外部端子的镀层上的晶须的生长，并且能够确保经济效益，降低成本，并且能够批量生产。

公开(公告)号：US07015590B2

公开(公告)日：2006-03-21

申请号：US10825199

申请日：2004-04-16

申请人： Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

发明人： Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

IPC分类号： H01L21/461 ,  H01L21/469

CPC分类号： H01L24/13 ,  B23K3/0607 ,  B23K3/0623 ,  H01L21/2885 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

摘要： A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusion from the contact pad and the ball pad are sized and arranged to have overlapping under portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

摘要翻译： 在布置在半导体芯片上的接触焊盘和布置在安装基板上的球垫之间形成加强焊料凸块连接器结构。 半导体芯片包括从中间层的表面向上延伸的至少一个增强突起。 安装基板包括从球垫向上延伸的至少一个加强突起，来自芯片和基板的突起被嵌入在焊料凸块连接器内。 在一些构造中，来自接触垫和球垫的加强突起的尺寸和布置成具有重叠的下部。 这些重叠部分可采取各种各样的构造，其允许突起重叠而不彼此接触，包括针阵列以及周围和被包围的元件的组合。 在每种构造中，加强突起将倾向于抑制裂纹形成和/或裂纹扩展，从而提高可靠性。

公开(公告)号：US20050285250A1

公开(公告)日：2005-12-29

申请号：US11089361

申请日：2005-03-25

申请人： Se-Young Jeong ,  Kang-Wook Lee

发明人： Se-Young Jeong ,  Kang-Wook Lee

IPC分类号： H01L23/12 ,  H01L23/02 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： The chip package includes a first and second semiconductor chip. The first semiconductor chip has a first connection structure that electrically connects to a bond pad on a first surface of the first semiconductor chip. The second semiconductor chip has a second connection structure. The second connection structure is electrically connected to a bond pad on a first surface of the second semiconductor chip and extends through the second semiconductor chip to a second surface of the second semiconductor chip. A portion of the second connection structure extending to the second surface of the second semiconductor chip is electrically connected to the first connection structure and formed of a harder material than the first connection structure.

摘要翻译： 芯片封装包括第一和第二半导体芯片。 第一半导体芯片具有电连接到第一半导体芯片的第一表面上的接合焊盘的第一连接结构。 第二半导体芯片具有第二连接结构。 第二连接结构电连接到第二半导体芯片的第一表面上的接合焊盘，并且延伸穿过第二半导体芯片到第二半导体芯片的第二表面。 延伸到第二半导体芯片的第二表面的第二连接结构的一部分电连接到第一连接结构，并且由比第一连接结构更硬的材料形成。

公开(公告)号：US08592991B2

公开(公告)日：2013-11-26

申请号：US13235369

申请日：2011-09-17

申请人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

发明人： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/00

CPC分类号： H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

摘要翻译： 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US08586477B2

公开(公告)日：2013-11-19

申请号：US13195128

申请日：2011-08-01

申请人： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

发明人： Se-young Jeong ,  Ho-jin Lee ,  Ho-geon Song ,  Jae-hyun Phee

IPC分类号： H01L21/44 ,  H01L21/00 ,  H01L23/04

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L23/481 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05614 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05552

摘要： A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

摘要翻译： 提供了具有贯通电极，半导体封装以及半导体封装的制造方法的半导体装置。 该方法包括制备包括掩埋通孔的衬底，所述埋入通孔在第一端具有第一表面，以及所述掩埋通孔从所述衬底的第一衬底表面延伸到所述衬底中; 平行化与第一衬底表面相对的衬底的第二衬底表面以通过在与第一端相对的埋置通孔的第二端处暴露第二通孔表面而形成通孔; 在通孔的暴露的第二通孔表面上形成导电覆盖层; 并且使所述第二衬底表面凹陷，使得所述通孔的至少第一部分延伸超出所述第二衬底表面。

公开(公告)号：US20120326307A1

公开(公告)日：2012-12-27

申请号：US13534792

申请日：2012-06-27

申请人： Se-young JEONG ,  Sang-sick PARK ,  Tae-gyeong CHUNG ,  Tae-je CHO

发明人： Se-young JEONG ,  Sang-sick PARK ,  Tae-gyeong CHUNG ,  Tae-je CHO

IPC分类号： H01L23/538 ,  H01L25/07

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06155 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements.

摘要翻译： 包括垂直堆叠的多个半导体芯片的堆叠半导体器件，分别形成有多个半导体芯片的半导体芯片并且分别形成在所述多个半导体芯片中的每一个的侧表面上的步骤的多个划线通道元件， 分别形成在所述多个半导体芯片和划线路元件中的每一个上的再分配元件，以及形成在所述多个半导体芯片中的每一个的侧表面上并电连接所述再分配元件的信号连接元件。

公开(公告)号：US20120056330A1

公开(公告)日：2012-03-08

申请号：US13186049

申请日：2011-07-19

申请人： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

发明人： Ho-Jin Lee ,  Sung-Dong Cho ,  Se-Young Jeong ,  Yeong-Lyeol Park ,  Sin-Woo Kang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.

摘要翻译： 半导体器件可以包括衬底和通孔。 衬底可以具有与第一表面相对的第一表面和第二表面，所述衬底包括形成在第一表面上的电路图案。 贯通电极穿透基板并且可以电连接到电路图案，所述通孔包括在基板的厚度方向上从第一表面延伸的第一插塞和在厚度方向上从第二表面延伸的第二插塞 以便连接到第一插头。