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公开(公告)号：US07151009B2
公开(公告)日：2006-12-19
申请号：US11038210
申请日：2005-01-21
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-min Sim
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.
摘要翻译： 提供了一种制造WLCSP器件的方法，其包括制备至少两个晶片，每个晶片具有多个对应的半导体芯片，每个半导体芯片具有形成在外围表面区域中的通孔，形成或施加固体粘合剂区域到中心表面 区域，堆叠多个晶片，并将设置在相邻晶片上的相应芯片与固体粘合剂区域连接并且通过相邻半导体芯片的电极相对应地连接，将堆叠的晶片分成单独的芯片堆叠封装，并将液体粘合剂注入到 相邻的半导体芯片结合在所得的芯片堆叠封装中。 通过降低相邻半导体芯片之间的空隙区域的可能性，预期根据本发明的示例性实施例的方法表现出改进的机械稳定性和可靠性。
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公开(公告)号：US20050280160A1
公开(公告)日：2005-12-22
申请号：US11038210
申请日：2005-01-21
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.
摘要翻译： 提供了一种制造WLCSP器件的方法，其包括制备至少两个晶片，每个晶片具有多个对应的半导体芯片，每个半导体芯片具有形成在外围表面区域中的通孔，形成或施加固体粘合剂区域到中心表面 区域，堆叠多个晶片，并将设置在相邻晶片上的相应芯片与固体粘合剂区域连接并且通过相邻半导体芯片的电极相对应地连接，将堆叠的晶片分成单独的芯片堆叠封装，并将液体粘合剂注入到 相邻的半导体芯片结合在所得的芯片堆叠封装中。 通过降低相邻半导体芯片之间的空隙区域的可能性，预期根据本发明的示例性实施例的方法表现出改进的机械稳定性和可靠性。
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公开(公告)号：US20050277293A1
公开(公告)日：2005-12-15
申请号：US11145994
申请日：2005-06-07
申请人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
发明人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
IPC分类号： H01L23/28 , C25D5/02 , C25D7/12 , H01L21/288 , H01L21/48 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/48
CPC分类号： C25D7/12 , C25D5/02 , H01L21/2885 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
摘要翻译： 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。
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公开(公告)号：US07524763B2
公开(公告)日：2009-04-28
申请号：US11145994
申请日：2005-06-07
申请人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
发明人： Soon-Bum Kim , Ung-Kwang Kim , Keum-Hee Ma , Young-Hee Song , Sung-Min Sim , Se-Yong Oh , Kang-Wook Lee , Se-Young Jeong
IPC分类号： H01L21/44
CPC分类号： C25D7/12 , C25D5/02 , H01L21/2885 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
摘要翻译： 制造晶片级芯片级封装的方法可包括形成穿透IC芯片的芯片焊盘的孔。 基底金属层可以形成在晶片的第一面上以覆盖孔的内表面。 电极金属层可以填充孔并在芯片垫上升起。 可以研磨晶片的第二面，使得孔中的电极金属层可以通过第二面露出。 通过电镀，可以在通过第二面暴露的电极金属层上形成电镀凸块。 可以选择性地去除贱金属层以隔离相邻的电极金属层。 可以沿着划线锯切晶片以将单独的封装与晶片分开。
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公开(公告)号：US20070200216A1
公开(公告)日：2007-08-30
申请号：US11703900
申请日：2006-12-19
申请人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
发明人： Soon-Bum Kim , Ung-Kwang Kim , Kang-Wook Lee , Se-Young Jeong , Young-Hee Song , Sung-Min Sim
IPC分类号： H01L23/02
CPC分类号： H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83194 , H01L2225/06513 , H01L2225/06541 , H01L2225/06582 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.
摘要翻译： 提供了一种芯片堆叠封装，其可以包括下半导体芯片，堆叠在下半导体芯片上的上半导体芯片，以及形成在下半导体芯片和上半导体芯片之间的空间中的至少一个粘合剂。 所述至少一种粘合剂可以包括第一粘合剂和第二粘合剂。 第一粘合剂可以形成在空间的一部分中，并且第二粘合剂可以形成在除了设置第一粘合剂的区域之外的空间中。 相邻的半导体芯片之间的空间可以被至少一个粘合剂完全填充。 因此，根据本发明的示例性实施例的芯片堆叠封装可以表现出改进的机械稳定性和可靠性。
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公开(公告)号：US07732319B2
公开(公告)日：2010-06-08
申请号：US11875713
申请日：2007-10-19
申请人： Se-Young Jeong , Sung-Min Sim , Soon-Bum Kim , In-Young Lee , Young-Hee Song
发明人： Se-Young Jeong , Sung-Min Sim , Soon-Bum Kim , In-Young Lee , Young-Hee Song
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05008 , H01L2224/05018 , H01L2224/05556 , H01L2224/05558 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
摘要翻译： 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。
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公开(公告)号：US07307342B2
公开(公告)日：2007-12-11
申请号：US11195361
申请日：2005-08-01
申请人： Se-Young Jeong , Sung-Min Sim , Soon-Bum Kim , In-Young Lee , Young-Hee Song
发明人： Se-Young Jeong , Sung-Min Sim , Soon-Bum Kim , In-Young Lee , Young-Hee Song
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05008 , H01L2224/05018 , H01L2224/05556 , H01L2224/05558 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
摘要翻译： 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。
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公开(公告)号：US20060060970A1
公开(公告)日：2006-03-23
申请号：US11195361
申请日：2005-08-01
申请人： Se-Young Jeong , Sung-Min Sim , Soon-Bum Kim , In-Young Lee , Young-Hee Song
发明人： Se-Young Jeong , Sung-Min Sim , Soon-Bum Kim , In-Young Lee , Young-Hee Song
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05008 , H01L2224/05018 , H01L2224/05556 , H01L2224/05558 , H01L2224/05571 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.
摘要翻译： 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。
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9.发明申请公开(公告)号：US20050104222A1
公开(公告)日：2005-05-19
申请号：US10944613
申请日：2004-09-20
申请人： Se-Young Jeong , Gu-Sung Kim , Nam-Seog Kim , Gi-Hwan Park , Se-Yong Oh , Soon-Bum Kim , In-Young Lee
发明人： Se-Young Jeong , Gu-Sung Kim , Nam-Seog Kim , Gi-Hwan Park , Se-Yong Oh , Soon-Bum Kim , In-Young Lee
IPC分类号： H01L23/28 , H01L21/60 , H01L23/16 , H01L23/31 , H01L23/485 , H01L23/498 , H05K3/34 , H01L23/48
CPC分类号： H01L24/13 , H01L23/16 , H01L23/3114 , H01L23/49838 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05647 , H01L2224/05655 , H01L2224/06102 , H01L2224/13076 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/1357 , H01L2224/13611 , H01L2224/1403 , H01L2224/14051 , H01L2224/14131 , H01L2224/14136 , H01L2224/14155 , H01L2224/16 , H01L2224/1601 , H01L2224/29011 , H01L2224/29013 , H01L2224/29076 , H01L2224/30155 , H01L2224/30156 , H01L2224/73103 , H01L2224/73203 , H01L2224/81141 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/351 , H05K3/3436 , H05K2201/094 , H05K2203/0465 , Y02P70/613 , H01L2924/00014 , H01L2924/01028 , H01L2924/01083 , H01L2224/13099 , H01L2924/00012 , H01L2924/3512 , H01L2924/00 , H01L2924/013
摘要： A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and electrically connected to the chip pads. And a solder bar may be provided on a portion of the protective layer. The solder bar may disperse thermal stress produced in the solder bumps. A metal core may be embedded within the solder bar. The flip chip device may be mounted on and flip-chip bonded to a substrate. The substrate may have land pads to which the solder bumps and the solder bar may be mechanically joined. The solder bar increases a joint area between the flip chip device and the substrate and reinforces solder connections therebetween.
摘要翻译： 倒装芯片器件可以具有其上可以设置有芯片焊盘和保护层的有源表面的半导体芯片。 可以在活性表面上提供焊料凸块并电连接到芯片焊盘。 并且可以在保护层的一部分上设置焊料条。 焊料棒可能会分散焊料凸点产生的热应力。 金属芯可以嵌入在焊条内。 倒装芯片器件可以安装在衬底上并倒装芯片结合到衬底上。 衬底可以具有焊盘，焊盘和焊条可以焊接到其上。 焊条增加了倒装芯片器件和衬底之间的接合面积，并加强了它们之间的焊接连接。
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公开(公告)号：US07214604B2
公开(公告)日：2007-05-08
申请号：US10973528
申请日：2004-10-25
申请人： Soon-Bum Kim , Se-Young Jeong , Se-Yong Oh , Nam-Seog Kim
发明人： Soon-Bum Kim , Se-Young Jeong , Se-Yong Oh , Nam-Seog Kim
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/02 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/1147 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1411 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/351 , H01L2924/0105 , H01L2924/00014 , H01L2924/00
摘要： Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.
摘要翻译： 提供一种制造超薄倒装芯片封装的方法。 在上述方法中，在半导体芯片的接合焊盘上形成下阻挡金属膜。 在下阻挡金属膜上形成三维结构化的焊料凸块，每个焊料凸块包括设置在棒部的端部的棒部和球部。 包括三维结构的焊料凸块的半导体芯片被结合到印刷电路板上的焊料层以完成倒装芯片封装。 根据本发明，通过采用三维结构化的焊料凸点，可以降低焊锡凸块的高度，从而提高超薄倒装芯片封装的可靠性。
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