Invention Application
US20080188052A1 Split-gate thin film storage NVM cell with reduced load-up/trap-up effects
有权
分流栅薄膜存储NVM单元,具有降低的加载/陷阱效应
- Patent Title: Split-gate thin film storage NVM cell with reduced load-up/trap-up effects
- Patent Title (中): 分流栅薄膜存储NVM单元,具有降低的加载/陷阱效应
-
Application No.: US11671809Application Date: 2007-02-06
-
Publication No.: US20080188052A1Publication Date: 2008-08-07
- Inventor: Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
- Applicant: Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
Public/Granted literature
- US07811886B2 Split-gate thin film storage NVM cell with reduced load-up/trap-up effects Public/Granted day:2010-10-12
Information query
IPC分类: