公开(公告)号：US20120273889A1

公开(公告)日：2012-11-01

申请号：US13548304

申请日：2012-07-13

申请人： Konstantin V. LOIKO ,  Toni D. VAN GOMPEL ,  Rode R. MORA ,  Michael D. TURNER ,  Brian A. WINSTEAD ,  Mark D. HALL

发明人： Konstantin V. LOIKO ,  Toni D. VAN GOMPEL ,  Rode R. MORA ,  Michael D. TURNER ,  Brian A. WINSTEAD ,  Mark D. HALL

IPC分类号： H01L29/772

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

公开(公告)号：US07960267B2

公开(公告)日：2011-06-14

申请号：US12414778

申请日：2009-03-31

申请人： Konstantin V. Loiko ,  Brian A. Winstead ,  Taras A. Kirichenko

发明人： Konstantin V. Loiko ,  Brian A. Winstead ,  Taras A. Kirichenko

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/7847 ,  H01L29/7881

摘要： A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.

摘要翻译： 在半导体层上制造半导体器件的方法包括：在半导体层上形成栅极电介质; 在所述栅极电介质上形成栅极材料层; 蚀刻栅极材料层以形成选择栅极; 形成在所述选择栅极上方和所述半导体层的一部分上方延伸的存储层; 在所述存储层上沉积非晶硅层; 蚀刻非晶硅层以形成控制栅极; 并对半导体器件进行退火以使非晶硅层结晶。

公开(公告)号：US07960243B2

公开(公告)日：2011-06-14

申请号：US11756231

申请日：2007-05-31

申请人： Brian A. Winstead ,  Konstantin V. Loiko ,  Voon-Yew Thean

发明人： Brian A. Winstead ,  Konstantin V. Loiko ,  Voon-Yew Thean

IPC分类号： H01L21/76 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823828 ,  H01L29/7833 ,  H01L29/7845

摘要： A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.

摘要翻译： 半导体器件（10）形成在半导体层（12）中。 在半导体层之上形成栅堆叠（16,18），并且包括第一层上的第一导电层（22）和第二层（24）。 第一层比第二层更具导电性并且为植入物提供更多的停止力。 物种（46）被植入第二层。 源极/漏极区域（52）形成在栅极堆叠的相对侧上的半导体层中。 栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。

公开(公告)号：US06249035B1

公开(公告)日：2001-06-19

申请号：US09480268

申请日：2000-01-11

申请人： Igor V. Peidous ,  Quek Kiok Boone Elgin ,  Konstantin V. Loiko ,  Tan Poh Suan ,  Vijai Kumar N. Chhagan

发明人： Igor V. Peidous ,  Quek Kiok Boone Elgin ,  Konstantin V. Loiko ,  Tan Poh Suan ,  Vijai Kumar N. Chhagan

IPC分类号： H01L2900

CPC分类号： H01L21/7621

摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of oxide punch though and the narrow oxide thinning effect.

摘要翻译： 一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。 掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。 掩模在其下边缘处使用薄的锥形氮化硅脚，以在氧化的早期阶段允许氧化物的标称膨胀，从而允许原位应力释放以及氧化物轮廓的平滑化。 脚的锥度提供了掩模刚度逐渐增加，因为在掩模边缘下进行氧化，允许在早期快速生长期期间具有最大的灵活性，随后在生长速率减慢的后期阶段增加刚度，由此抑制鸟的渗透 喙。 负责位错生成的剪切应力减少了五十倍。 这种应力降低伴随着表面形貌的改善以及氧化物冲击的抑制以及窄的氧化物稀化效应。

公开(公告)号：US5894059A

公开(公告)日：1999-04-13

申请号：US866776

申请日：1997-05-30

申请人： Igor V. Peidous ,  Konstantin V. Loiko ,  Elgin Quek ,  David Yeo Yong Hock

发明人： Igor V. Peidous ,  Konstantin V. Loiko ,  Elgin Quek ,  David Yeo Yong Hock

IPC分类号： H01L21/033 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/0332 ,  H01L21/76202 ,  Y10S438/95

摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

公开(公告)号：US09343314B2

公开(公告)日：2016-05-17

申请号：US14291359

申请日：2014-05-30

申请人： Konstantin V. Loiko ,  Brian A. Winstead

发明人： Konstantin V. Loiko ,  Brian A. Winstead

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7883 ,  H01L29/792

摘要： A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

摘要翻译： 一种制造分离栅极非易失性存储器（NVM）的方法包括在衬底上形成电荷存储层，沉积第一导电层和沉积覆盖层。 将这些层图案化以形成控制栅叠层。 第二导电层沉积在衬底上并被图案化以将第二导电层的第一部分留在控制栅极堆叠的一部分上并且邻近控制栅极堆叠的第一侧。 第二导电层和控制栅极堆叠的第一部分被平坦化以从第二导电层的第一部分留出虚拟选择栅极，其中第一导电层的剩余部分的顶表面相对于顶部 虚拟选通门的表面。 虚拟选择栅极被包括金属的选择栅极替代。

公开(公告)号：US20150348786A1

公开(公告)日：2015-12-03

申请号：US14291359

申请日：2014-05-30

申请人： KONSTANTIN V. LOIKO ,  BRIAN A. WINSTEAD

发明人： KONSTANTIN V. LOIKO ,  BRIAN A. WINSTEAD

IPC分类号： H01L21/28 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7883 ,  H01L29/792

摘要： A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

摘要翻译： 一种制造分离栅极非易失性存储器（NVM）的方法包括在衬底上形成电荷存储层，沉积第一导电层和沉积覆盖层。 将这些层图案化以形成控制栅叠层。 第二导电层沉积在衬底上并被图案化以将第二导电层的第一部分留在控制栅极堆叠的一部分上并且邻近控制栅极堆叠的第一侧。 第二导电层和控制栅极堆叠的第一部分被平坦化以从第二导电层的第一部分留出虚拟选择栅极，其中第一导电层的剩余部分的顶表面相对于顶部 虚拟选通门的表面。 虚拟选择栅极被包括金属的选择栅极替代。

公开(公告)号：US09202930B2

公开(公告)日：2015-12-01

申请号：US13111580

申请日：2011-05-19

申请人： Konstantin V. Loiko ,  Brian A. Winstead ,  Mehul D. Shroff

发明人： Konstantin V. Loiko ,  Brian A. Winstead ,  Mehul D. Shroff

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  G11C16/04

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  G11C16/0425 ,  H01L29/42332 ,  H01L29/66825

摘要： A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.

摘要翻译： 制造非易失性存储单元的方法包括形成多个离散存储元件。 在离散存储元件之间形成拉伸介电层，并向分立存储元件提供横向拉伸应力。 在离散存储元件上形成栅极。

公开(公告)号：US08236638B2

公开(公告)日：2012-08-07

申请号：US11788184

申请日：2007-04-18

申请人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

发明人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

公开(公告)号：US07821055B2

公开(公告)日：2010-10-26

申请号：US12414763

申请日：2009-03-31

申请人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

发明人： Konstantin V. Loiko ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Taras A. Kirichenko ,  Brian A. Winstead

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42328 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/7881

摘要： A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

摘要翻译： 在半导体层上制造半导体器件的方法包括在栅极电介质上形成栅极电介质和栅极材料的第一层。 第一层被蚀刻以在半导体层的第一部分上移除第一层栅极材料的一部分并留下选择栅极部分。 存储层形成在选择栅极部分上方和半导体层的第一部分之上。 在存储层上形成第二层栅极材料层。 第二层栅极材料被蚀刻以在选择栅极部分的第一部分上移除第二层栅极材料的第一部分。 选择栅极的第一部分的一部分被蚀刻以留下L形选择结构。 结果是具有L形选择栅极的存储单元。