发明申请
US20080188052A1 Split-gate thin film storage NVM cell with reduced load-up/trap-up effects
有权
分流栅薄膜存储NVM单元,具有降低的加载/陷阱效应
- 专利标题: Split-gate thin film storage NVM cell with reduced load-up/trap-up effects
- 专利标题(中): 分流栅薄膜存储NVM单元,具有降低的加载/陷阱效应
-
申请号: US11671809申请日: 2007-02-06
-
公开(公告)号: US20080188052A1公开(公告)日: 2008-08-07
- 发明人: Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
- 申请人: Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
公开/授权文献
信息查询
IPC分类: