发明申请
- 专利标题: METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS
- 专利标题(中): 形成低应力电介质膜的方法
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申请号: US12835574申请日: 2010-07-13
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公开(公告)号: US20120015113A1公开(公告)日: 2012-01-19
- 发明人: Zhong Qiang Hua , Lei Luo , Manuel A. Hernandez , Shankar Venkataraman
- 申请人: Zhong Qiang Hua , Lei Luo , Manuel A. Hernandez , Shankar Venkataraman
- 申请人地址: US CA Santa Clara
- 专利权人: Applied Materials, Inc.
- 当前专利权人: Applied Materials, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: C23C16/513
- IPC分类号: C23C16/513
摘要:
A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.
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