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    Conformality of oxide layers along sidewalls of deep vias
    2.
    发明授权
    Conformality of oxide layers along sidewalls of deep vias 有权
    深层通孔侧壁氧化层的一致性

    公开(公告)号：US08404583B2

    公开(公告)日：2013-03-26

    申请号：US13035034

    申请日：2011-02-25

    申请人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    发明人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    IPC分类号： H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/76898

    摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.

    摘要翻译： 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层，并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积（CVD）工艺形成氧化物层，其中通孔底部的氧化物层的厚度为厚度的至少约50％ 在氮化物层的顶表面处的氧化物层。

    METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS
    3.
    发明申请
    METHODS FOR FORMING LOW STRESS DIELECTRIC FILMS 审中-公开
    形成低应力电介质膜的方法

    公开(公告)号：US20120015113A1

    公开(公告)日：2012-01-19

    申请号：US12835574

    申请日：2010-07-13

    申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

    发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Shankar Venkataraman

    IPC分类号： C23C16/513

    CPC分类号： C23C16/513 ,  C23C16/401 ,  C23C16/44

    摘要： A method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.

    摘要翻译： 在衬底上形成多层氧化硅膜的方法包括执行沉积循环，其包括使用热化学气相沉积（CVD）工艺沉积氧化硅层，并使用等离子体增强化学气相沉积法沉积氧化硅层（ PECVD）过程。 沉积循环重复规定次数以形成包含使用热CVD工艺形成的多个氧化硅层和使用PECVD工艺形成的多个氧化硅层的多层氧化硅膜。 使用热CVD工艺形成的每个氧化硅层与使用PECVD工艺形成的至少一个氧化硅层相邻。

    CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS
    4.
    发明申请
    CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS 有权
    深层六角形氧化层的一致性

    公开(公告)号：US20110223760A1

    公开(公告)日：2011-09-15

    申请号：US13035034

    申请日：2011-02-25

    申请人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    发明人： Zhong Qiang Hua ,  Manuel A. Hernandez ,  Lei Luo ,  Kedar Sapre

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76898

    摘要： A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.

    摘要翻译： 在半导体衬底中的通孔侧壁改善氧化物层的保形性的方法包括在半导体衬底的上表面上形成氮化物层，并形成延伸穿过氮化物层并进入半导体衬底的通孔。 通孔可以具有距离氮化物层的顶表面至少约50μm的深度和在氮化物层的顶表面处的小于约10μm的开口。 该方法还包括在氮化物层上并沿着通孔的侧壁和底部形成氧化物层。 可以在小于约450℃的温度下使用热化学气相沉积（CVD）工艺形成氧化物层，其中通孔底部的氧化物层的厚度为厚度的至少约50％ 在氮化物层的顶表面处的氧化物层。

    Internal balanced coil for inductively coupled high density plasma processing chamber
    5.
    发明授权
    Internal balanced coil for inductively coupled high density plasma processing chamber 有权
    用于电感耦合高密度等离子体处理室的内部平衡线圈

    公开(公告)号：US07789993B2

    公开(公告)日：2010-09-07

    申请号：US11670662

    申请日：2007-02-02

    申请人： Robert Chen ,  Canfeng Lai ,  Xinglong Chen ,  Weiyi Luo ,  Zhong Qiang Hua ,  Siqing Lu ,  Muhammad Rasheed ,  Qiwei Liang ,  Dmitry Lubomirsky ,  Ellie Y. Yieh

    发明人： Robert Chen ,  Canfeng Lai ,  Xinglong Chen ,  Weiyi Luo ,  Zhong Qiang Hua ,  Siqing Lu ,  Muhammad Rasheed ,  Qiwei Liang ,  Dmitry Lubomirsky ,  Ellie Y. Yieh

    IPC分类号： C23C16/00 ,  H01L21/306

    CPC分类号： H01J37/321

    摘要： A coil is provided for use in a semiconductor processing system to generate a plasma with a magnetic field in a chamber. The coil comprises a first coil segment, a second coil segment and an internal balance capacitor. The first coils segment has a first end and a second end. The first end of the coil segment is adapted to connect to a power source. The second coil segment has a first and second end. The second end of the first coil segment is adapted to connect to an external balance capacitor. The internal balance capacitor is connected in series between the second end of the first coil segment and the first end of the second coil segment. The internal balance capacitor and the coil segments are adapted to provide a voltage peak along the first coil segment substantially aligned with a virtual ground along the second coil segment.

    摘要翻译： 提供一种用于半导体处理系统中的线圈以在腔室中产生具有磁场的等离子体。 线圈包括第一线圈段，第二线圈段和内部平衡电容器。 第一线圈段具有第一端和第二端。 线圈段的第一端适于连接到电源。 第二线圈段具有第一和第二端。 第一线圈段的第二端适于连接到外部平衡电容器。 内部平衡电容器串联连接在第一线圈段的第二端和第二线圈段的第一端之间。 内部平衡电容器和线圈段适于沿着第一线圈段提供基本上与第二线圈段的虚拟接地对准的电压峰值。

    METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS
    8.
    发明申请
    METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS 审中-公开
    形成低水分电介质膜的方法

    公开(公告)号：US20120058281A1

    公开(公告)日：2012-03-08

    申请号：US13041201

    申请日：2011-03-04

    申请人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Zhitao Cao ,  Kedar Sapre ,  Ajay Bhatnagar

    发明人： Zhong Qiang Hua ,  Lei Luo ,  Manuel A. Hernandez ,  Zhitao Cao ,  Kedar Sapre ,  Ajay Bhatnagar

    IPC分类号： B05D5/00 ,  C23C16/56 ,  C23C16/50 ,  C23C16/40 ,  C23C16/44

    CPC分类号： H01L21/02164 ,  C23C16/40 ,  C23C16/56 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362

    摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.

    摘要翻译： 在衬底上形成预金属电介质（PMD）层或金属间电介质（IMD）层的方法包括将衬底放置在化学气相沉积（CVD）处理室中，并在衬底上形成第一氧化物层 CVD处理室。 第一氧化物层使用热CVD工艺在约450℃或更低的温度和低于大气压的压力下形成。 该方法还包括在CVD处理室中的第一氧化物层上形成第二氧化物层。 使用等离子体增强化学气相沉积（PECVD）工艺在约450℃或更低的温度和低于大气压的压力下形成第二氧化物层。 在形成第一氧化物层和第二氧化物层期间，衬底保留在CVD处理室中。

    Remote plasma clean process with cycled high and low pressure clean steps
    9.
    发明授权
    Remote plasma clean process with cycled high and low pressure clean steps 失效
    远程等离子清洁工艺，循环高低压清洁步骤

    公开(公告)号：US07967913B2

    公开(公告)日：2011-06-28

    申请号：US12508381

    申请日：2009-07-23

    申请人： Zhong Qiang Hua ,  Sanjay Kamath ,  Young S. Lee ,  Ellie Y. Yieh ,  Hien-Minh Huu Le ,  Anjana M. Patel ,  Sudhir R. Gondhalekar

    发明人： Zhong Qiang Hua ,  Sanjay Kamath ,  Young S. Lee ,  Ellie Y. Yieh ,  Hien-Minh Huu Le ,  Anjana M. Patel ,  Sudhir R. Gondhalekar

    IPC分类号： B08B6/00

    CPC分类号： B08B7/0035 ,  C23C16/4405

    摘要： A remote plasma process for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber after processing a substrate disposed in the substrate processing chamber. In one embodiment, the substrate is transferred out of the substrate processing chamber and a flow of a fluorine-containing etchant gas is introduced into a remote plasma source where reactive species are formed. A continuous flow of the reactive species from the remote plasmas source to the substrate processing chamber is generated while a cycle of high and low pressure clean steps is repeated. During the high pressure clean step, reactive species are flown into the substrate processing chamber while pressure within the substrate processing chamber is maintained between 4-15 Torr. During the low pressure clean step, reactive species are flown into the substrate processing chamber while reducing the pressure of the substrate processing chamber by at least 50 percent of a high pressure reached in the high pressure clean step.

    摘要翻译： 一种远程等离子体处理，用于在处理设置在基板处理室中的基板之后从基板处理室的一个或多个内表面去除不需要的沉积物。 在一个实施例中，将衬底转移出衬底处理室，并且将含氟蚀刻剂气体的流引入形成反应性物质的远程等离子体源中。 产生反应物质从远程等离子体源到基底处理室的连续流动，同时重复高低压清洁步骤的循环。 在高压清洁步骤期间，反应性物质流入基板处理室，同时基板处理室内的压力保持在4-15Torr之间。 在低压清洁步骤期间，将反应性物质流入基板处理室，同时将基板处理室的压力降低至高压清洁步骤达到的至少50％的高压。

    METHOD FOR DOPING NON-PLANAR TRANSISTORS
    10.
    发明申请
    METHOD FOR DOPING NON-PLANAR TRANSISTORS 失效
    非平面晶体管的方法

    公开(公告)号：US20110129990A1

    公开(公告)日：2011-06-02

    申请号：US12843726

    申请日：2010-07-26

    申请人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

    发明人： Tushar V. Mandrekar ,  Shankar Venkataraman ,  Zhong Qiang Hua ,  Manuel A. Hernandez

    IPC分类号： H01L21/22

    CPC分类号： H01L21/2256 ,  H01L29/66803

    摘要： Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching.

    摘要翻译： 公开了通过在非平面结构上形成共形掺杂的硅玻璃层来掺杂非平面结构的方法。 将其上形成有非平面结构的基板放置在化学气相沉积处理室中以沉积掺杂玻璃（例如BSG或PSG）的共形SACVD层。 然后将衬底暴露于RTP或激光退火步骤以将掺杂剂扩散到非平面结构中，然后通过蚀刻去除掺杂的玻璃层。