发明申请
- 专利标题： Vertical NPNP Structure In a Triple Well CMOS Process
- 专利标题（中）： 三井CMOS工艺中的垂直NPNP结构
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申请号： US12954155申请日： 2010-11-24
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公开(公告)号： US20120126285A1公开(公告)日： 2012-05-24
- 发明人: John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
- 申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L29/74
- IPC分类号： H01L29/74 ; G06F17/50 ; H01L21/332
摘要：
A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
公开/授权文献
- US08299533B2 Vertical NPNP structure in a triple well CMOS process 公开/授权日：2012-10-30
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