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    Electrical overstress protection circuit
    1.
    发明授权
    Electrical overstress protection circuit 有权
    电气过载保护电路

    公开(公告)号：US08363367B2

    公开(公告)日：2013-01-29

    申请号：US12632015

    申请日：2009-12-07

    Applicant: John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    Inventor： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Mujahid Muhammad

    IPC: H02H9/00

    CPC classification number: H01L27/0251 ,  G06F17/5045

    Abstract: A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.

    Abstract translation: 提供了一种用于电力过应力（EOS）保护的半导体电路。 半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。 连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。 特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。 可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

    High voltage ESD power clamp
    5.
    发明授权
    High voltage ESD power clamp 失效
    高压ESD电源钳

    公开(公告)号：US07203045B2

    公开(公告)日：2007-04-10

    申请号：US10711748

    申请日：2004-10-01

    Applicant: Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mahmoud A. Mousa ,  Mujahid Muhammad ,  Christopher S. Putnam

    Inventor： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mahmoud A. Mousa ,  Mujahid Muhammad ,  Christopher S. Putnam

    IPC: H02H3/20 ,  H02H3/22 ,  H02H9/00 ,  H02H9/04

    CPC classification number: H01L27/0266 ,  H03K17/08142

    Abstract: A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.

    Abstract translation: 为静电放电电源钳提供一种用于高压电源的结构和装置。 功率钳包括晶体管器件网络，例如串联布置在电源轨和接地轨之间的nFET。 第一晶体管器件被偏置成部分导通状态，因此，两个器件都不会看到电源轨和接地轨之间的全电压电位。 因此，功率钳可以在高于晶体管器件的天然电压的电压环境中工作。 此外，第二晶体管器件由用作触发器的RC网络控制，该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小，从而在集成电路上需要小的空间。 打开后，夹具可能会导通快速导通时间，并长时间传导电流。

    Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time
    6.
    发明授权
    Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time 失效
    混合耐压静电放电保护可控硅整流器，增加开启时间

    公开(公告)号：US07005686B1

    公开(公告)日：2006-02-28

    申请号：US11161184

    申请日：2005-07-26

    Applicant: Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Andreas D. Stricker ,  Min Woo

    Inventor： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Andreas D. Stricker ,  Min Woo

    IPC: H01L29/66 ,  H01L21/33

    CPC classification number: H01L27/0262 ,  H01L29/87

    Abstract: Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.

    Abstract translation: 公开了一种用于增加可控硅整流器中的衬底电阻以减少导通时间的方法，使得可控硅整流器可以用作有效的静电放电保护装置，以防止HBM，MM和CDM放电事件。 此外，公开了一种改进的SCR结构，其适于用作静电放电装置，以通过将静电放电电流直接递送到接地轨来防止人体模型事件。 改进的SCR结构包含用于增加衬底电阻并因此减少导通时间的各种特征。 这些特征包括作为电流流动的障碍的第二n阱，连接到第二n阱的下部的共平面埋入n波段之间的窄电流流动通道，零阈值电压区域和 外部电阻电连接在SCR和接地导轨之间。

    PFET-BASED ESD PROTECTION STRATEGY FOR IMPROVED EXTERNAL LATCH-UP ROBUSTNESS
    7.
    发明申请
    PFET-BASED ESD PROTECTION STRATEGY FOR IMPROVED EXTERNAL LATCH-UP ROBUSTNESS 审中-公开
    基于PFET的ESD保护策略，用于改进外部锁定稳定性

    公开(公告)号：US20050045952A1

    公开(公告)日：2005-03-03

    申请号：US10604922

    申请日：2003-08-27

    Applicant: Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

    Inventor： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

    IPC: H01L21/336 ,  H01L27/02

    CPC classification number: H01L27/0266

    Abstract: A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.

    Abstract translation: 公开了一种具有改进的闩锁鲁棒性的防静电放电（ESD）的方法和装置，其具有硅化物阻挡的p型场效应晶体管。 晶体管具有小于其栅极氧化物的击穿电压的快速恢复电压。 晶体管是集成电路的一部分，并且耦合到没有直接连接到其的n扩散的I / O焊盘。 给定的集成电路可以采用根据本发明配置的一个或多个与集成电路内的一个或多个I / O焊盘相关联的晶体管。

    ESD field-effect transistor and integrated diffusion resistor
    9.
    发明授权
    ESD field-effect transistor and integrated diffusion resistor 有权
    ESD场效应晶体管和集成扩散电阻

    公开(公告)号：US08513738B2

    公开(公告)日：2013-08-20

    申请号：US13188094

    申请日：2011-07-21

    Applicant: John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    Inventor： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC: H01L23/60

    CPC classification number: H01L29/41775 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

    Abstract translation: 静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。 第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。 可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。 静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

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