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    Stress enhanced junction engineering for latchup SCR
    3.
    发明授权
    Stress enhanced junction engineering for latchup SCR 有权
    应力增强连接工程用于闭锁SCR

    公开(公告)号：US08377754B1

    公开(公告)日：2013-02-19

    申请号：US13269819

    申请日：2011-10-10

    Applicant: John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra

    Inventor： John B. Campi, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra

    IPC: H01L21/332

    CPC classification number: H01L29/66068 ,  H01L29/66393 ,  H01L29/7436

    Abstract: A method of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area; and removing the mask.

    Abstract translation: 一种形成包括闭锁硅可控整流器（SCR）的IC器件的方法包括在衬底的顶表面上形成掩模，其中所述掩模覆盖所述衬底的第一部分并且暴露所述衬底的位于 在衬底上的n阱和p阱中的一个; 蚀刻所述基板的暴露的第二部分以形成蚀刻区域; 通过选择性外延沉积在蚀刻区域中形成闭锁SCR的应力工程结; 并取下面罩。

    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology
    4.
    发明授权
    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology 有权
    低触发电压静电放电NFET三阱CMOS技术

    公开(公告)号：US08350329B2

    公开(公告)日：2013-01-08

    申请号：US12907105

    申请日：2010-10-19

    Applicant: John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    Inventor： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC: H01L23/60 ,  H01L21/8238

    CPC classification number: H01L27/0274

    Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

    Abstract translation: 用于集成电路的静电放电（ESD）保护装置包括形成在第二极性类型的衬底中的第一极性类型的掩埋层。 第二极性类型的阱区形成在掩埋层的上方。 在阱区内形成第一极性类型的FET。 第一极性类型的内部一对浅阱设置在FET的源极和漏极扩散区附近，内部一对浅阱具有使得内部一对浅井的底部高于 埋层 第一极性类型的一对深阱对向下延伸到掩埋层的顶部，使得外部一对深阱和掩埋层限定第二极性类型的阱区的周边。

    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology
    5.
    发明申请
    Low trigger voltage electrostatic discharge NFET in triple well CMOS technology 有权
    低触发电压静电放电NFET三阱CMOS技术

    公开(公告)号：US20120091530A1

    公开(公告)日：2012-04-19

    申请号：US12907105

    申请日：2010-10-19

    Applicant: John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    Inventor： John B. Campi, JR. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L27/0274

    Abstract: An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

    Abstract translation: 用于集成电路的静电放电（ESD）保护装置包括形成在第二极性类型的衬底中的第一极性类型的掩埋层。 第二极性类型的阱区形成在掩埋层的上方。 在阱区内形成第一极性类型的FET。 第一极性类型的内部一对浅阱设置在FET的源极和漏极扩散区附近，内部一对浅阱具有使得内部一对浅井的底部高于 埋层 第一极性类型的一对深阱对向下延伸到掩埋层的顶部，使得外部一对深阱和掩埋层限定第二极性类型的阱区的周边。

    ESD field-effect transistor and integrated diffusion resistor
    7.
    发明授权
    ESD field-effect transistor and integrated diffusion resistor 有权
    ESD场效应晶体管和集成扩散电阻

    公开(公告)号：US08513738B2

    公开(公告)日：2013-08-20

    申请号：US13188094

    申请日：2011-07-21

    Applicant: John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    Inventor： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

    IPC: H01L23/60

    CPC classification number: H01L29/41775 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

    Abstract translation: 静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。 第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。 可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。 静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

    Personal stress level monitor and systems and methods for using same
    10.
    发明申请
    Personal stress level monitor and systems and methods for using same 审中-公开
    个人压力水平监视器及其使用方法

    公开(公告)号：US20050154264A1

    公开(公告)日：2005-07-14

    申请号：US10753853

    申请日：2004-01-08

    Applicant: Kellie Lecompte ,  Ivan Milman ,  Rahul Mishra ,  Karthikeyan Ramamoorthy

    Inventor： Kellie Lecompte ,  Ivan Milman ,  Rahul Mishra ,  Karthikeyan Ramamoorthy

    IPC: A61B5/00 ,  A61B5/02 ,  A61B5/024 ,  A61B5/053 ,  A61B10/00 ,  G06F17/00

    CPC classification number: A61B5/486 ,  A61B5/0002 ,  A61B5/02 ,  A61B5/024 ,  A61B5/0533 ,  A61B5/4884

    Abstract: A mechanism to monitor an individual's level of stress in his or her home or workplace is provided. Unobtrusive physiologic stress senses are used in combination with a wireless link and a personal computer or other intelligent device to monitor the user's stress level. Based on a user profile and the user's baseline stress indicators, one or more stress-reducing activities are presented to the user. Additionally, if a user is in a stress-sensitive population, for example, persons with a pre-existing hypertension, the user may selectively enable additional alerts.

    Abstract translation: 提供了监测个人在家中或工作场所的压力水平的机制。 不引人注意的生理应激感与无线链路和个人计算机或其他智能设备结合使用以监视用户的压力水平。 基于用户简档和用户的基准压力指标，向用户呈现一个或多个减轻压力的活动。 此外，如果用户处于压力敏感的人群中，例如，具有预先存在的高血压的人，则用户可以选择性地启用附加警报。

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