发明申请
US20120187584A1 Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers
有权
用于形成半导体封装的半导体器件和方法，其具有具有不同CTE绝缘层的半导体晶片的堆叠互连结构
- 专利标题： Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers
- 专利标题（中）： 用于形成半导体封装的半导体器件和方法，其具有具有不同CTE绝缘层的半导体晶片的堆叠互连结构
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申请号： US13164015申请日： 2011-06-20
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公开(公告)号： US20120187584A1公开(公告)日： 2012-07-26
- 发明人: Yaojian Lin , Kang Chen , Yu Gu , Wei Meng , Chee Siang Ong
- 申请人： Yaojian Lin , Kang Chen , Yu Gu , Wei Meng , Chee Siang Ong
- 申请人地址： SG Singapore
- 专利权人： STATS CHIPPAC, LTD.
- 当前专利权人： STATS CHIPPAC, LTD.
- 当前专利权人地址： SG Singapore
- 主分类号： H01L23/28
- IPC分类号： H01L23/28 ; H01L21/56
摘要：
A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
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