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1.发明申请Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers 有权用于形成半导体封装的半导体器件和方法，其具有具有不同CTE绝缘层的半导体晶片的堆叠互连结构公开(公告)号：US20120187584A1
公开(公告)日：2012-07-26
申请号：US13164015
申请日：2011-06-20
申请人： Yaojian Lin , Kang Chen , Yu Gu , Wei Meng , Chee Siang Ong
发明人： Yaojian Lin , Kang Chen , Yu Gu , Wei Meng , Chee Siang Ong
CPC分类号： H01L23/562 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/29 , H01L23/3107 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2924/01029 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
摘要翻译： 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 在管芯和密封剂上形成第一绝缘层。 第一绝缘层通过多个停留周期固化，以增强与管芯和密封剂的粘合性。 在第一绝缘层上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 第二绝缘层通过多个停留循环固化，以增强与第一绝缘层和第一导电层的粘合性。 在第二绝缘层和第一导电层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 第一，第二和第三绝缘层具有不同的CTE。 第二绝缘层或第三绝缘层固化至致密状态以阻止水分。
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2.发明授权Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers 有权半导体器件和半导体封装的形成方法，其具有在具有不同CTE绝缘层的半导体管芯上的积层互连结构公开(公告)号：US08492203B2
公开(公告)日：2013-07-23
申请号：US13164015
申请日：2011-06-20
申请人： Yaojian Lin , Kang Chen , Yu Gu , Wei Meng , Chee Siang Ong
发明人： Yaojian Lin , Kang Chen , Yu Gu , Wei Meng , Chee Siang Ong
CPC分类号： H01L23/562 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/29 , H01L23/3107 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2924/01029 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
摘要翻译： 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 在管芯和密封剂上形成第一绝缘层。 第一绝缘层通过多个停留周期固化，以增强与管芯和密封剂的粘合性。 在第一绝缘层上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 第二绝缘层通过多个停留循环固化，以增强对第一绝缘层和第一导电层的粘合性。 在第二绝缘层和第一导电层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 第一，第二和第三绝缘层具有不同的CTE。 第二绝缘层或第三绝缘层固化至致密状态以阻止水分。
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3.发明申请SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF 有权半导体器件和形成绝缘层的半导体器件的应力消除形成方法公开(公告)号：US20130113092A9
公开(公告)日：2013-05-09
申请号：US13333739
申请日：2011-12-21
申请人： Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
发明人： Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
CPC分类号： H01L23/3114 , H01L21/31 , H01L21/56 , H01L21/568 , H01L21/768 , H01L21/76877 , H01L21/78 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/522 , H01L23/528 , H01L23/5389 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/48091 , H01L2224/73265 , H01L2224/94 , H01L2224/96 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01043 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10156 , H01L2924/10157 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2224/19 , H01L2924/00014 , H01L2924/00 , H01L2224/03 , H01L2924/00012 , H01L2224/214
摘要： A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
摘要翻译： 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。
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4.发明授权Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer 有权半导体器件和形成强大的扇出封装的方法，包括垂直互连和机械支撑层公开(公告)号：US09082780B2
公开(公告)日：2015-07-14
申请号：US13428439
申请日：2012-03-23
申请人： Yaojian Lin , Kang Chen , Yu Gu
发明人： Yaojian Lin , Kang Chen , Yu Gu
IPC分类号： H01L21/00 , H01L21/56 , H01L23/498 , H01L23/00 , H01L25/10 , H01L23/538
CPC分类号： H01L21/563 , H01L21/568 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2224/19 , H01L2924/00012 , H01L2224/03
摘要： A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.
摘要翻译： 半导体器件具有半导体管芯。 围绕半导体管芯沉积密封剂。 具有导电凸块的互连结构形成在密封剂和半导体管芯上。 机械支撑层形成在互连结构上并且围绕导电凸块。 机械支撑层形成在半导体管芯的拐角上并且在互连结构的拐角上。 通过延伸到互连结构的密封剂形成开口。 导电材料沉积在开口内以形成导电的通过密封剂通过（TEV）电连接到互连结构。 将半导体器件安装到TEV并在半导体管芯上方形成封装封装（PoP）器件。 在与互连结构相对的密封剂上形成翘曲平衡层。
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5.发明申请Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units 有权具有PWB垂直互连单元的扇出PoP设备的半导体方法和装置公开(公告)号：US20130249115A1
公开(公告)日：2013-09-26
申请号：US13429119
申请日：2012-03-23
申请人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
发明人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
CPC分类号： H01L23/481 , H01L21/4846 , H01L21/486 , H01L21/56 , H01L21/563 , H01L21/568 , H01L23/13 , H01L23/28 , H01L23/49816 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/5389 , H01L24/10 , H01L24/19 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/16225 , H01L2224/24155 , H01L2224/24195 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1035 , H01L2924/00011 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/81805 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。
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6.发明申请Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief 有权半导体器件和形成用于应力释放的半导体晶片上的绝缘层的方法公开(公告)号：US20120112340A1
公开(公告)日：2012-05-10
申请号：US13333739
申请日：2011-12-21
申请人： Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
发明人： Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
CPC分类号： H01L23/3114 , H01L21/31 , H01L21/56 , H01L21/568 , H01L21/768 , H01L21/76877 , H01L21/78 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/522 , H01L23/528 , H01L23/5389 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/48091 , H01L2224/73265 , H01L2224/94 , H01L2224/96 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01043 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10156 , H01L2924/10157 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2224/19 , H01L2924/00014 , H01L2924/00 , H01L2224/03 , H01L2924/00012 , H01L2224/214
摘要： A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
摘要翻译： 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。
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7.发明申请Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units 审中-公开具有PWB垂直互连单元的扇出PoP设备的半导体方法公开(公告)号：US20130249101A1
公开(公告)日：2013-09-26
申请号：US13477982
申请日：2012-05-22
申请人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
发明人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
CPC分类号： H01L23/3121 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。
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8.发明授权Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units 有权用PWB垂直互连单元形成扇出PoP器件的半导体方法和装置公开(公告)号：US08810024B2
公开(公告)日：2014-08-19
申请号：US13429119
申请日：2012-03-23
申请人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
发明人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
CPC分类号： H01L23/481 , H01L21/4846 , H01L21/486 , H01L21/56 , H01L21/563 , H01L21/568 , H01L23/13 , H01L23/28 , H01L23/49816 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/5389 , H01L24/10 , H01L24/19 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/16225 , H01L2224/24155 , H01L2224/24195 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1035 , H01L2924/00011 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2224/81805 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。
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公开(公告)号：US08456002B2
公开(公告)日：2013-06-04
申请号：US13333739
申请日：2011-12-21
申请人： Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
发明人： Yaojian Lin , Pandi C. Marimuthu , Kang Chen , Hin Hwa Goh , Yu Gu , Il Kwon Shim , Rui Huang , Seng Guan Chow , Jianmin Fang , Xia Feng
IPC分类号： H01L23/52
CPC分类号： H01L23/3114 , H01L21/31 , H01L21/56 , H01L21/568 , H01L21/768 , H01L21/76877 , H01L21/78 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/522 , H01L23/528 , H01L23/5389 , H01L23/562 , H01L24/19 , H01L24/20 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/48091 , H01L2224/73265 , H01L2224/94 , H01L2224/96 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01043 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10156 , H01L2924/10157 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2224/19 , H01L2924/00014 , H01L2924/00 , H01L2224/03 , H01L2924/00012 , H01L2224/214
摘要： A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
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10.发明申请Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer 有权半导体器件和形成包括垂直互连和机械支撑层的鲁棒扇出封装的方法公开(公告)号：US20130249106A1
公开(公告)日：2013-09-26
申请号：US13428439
申请日：2012-03-23
申请人： Yaojian Lin , Kang Chen , Yu Gu
发明人： Yaojian Lin , Kang Chen , Yu Gu
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L21/563 , H01L21/568 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/5389 , H01L24/19 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2224/19 , H01L2924/00012 , H01L2224/03
摘要： A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.
摘要翻译： 半导体器件具有半导体管芯。 围绕半导体管芯沉积密封剂。 具有导电凸块的互连结构形成在密封剂和半导体管芯上。 机械支撑层形成在互连结构上并且围绕导电凸块。 机械支撑层形成在半导体管芯的拐角上并且在互连结构的拐角上。 通过延伸到互连结构的密封剂形成开口。 导电材料沉积在开口内以形成导电的通过密封剂通过（TEV）电连接到互连结构。 将半导体器件安装到TEV并在半导体管芯上方形成封装封装（PoP）器件。 在与互连结构相对的密封剂上形成翘曲平衡层。
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